Test Economics

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Test Economics

• By Abdelghani Renbi
• PhD Student
• Luleå University of Technology
• EISLAB (Embedded Internet Systems Laboratory)

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Why Test Economics

• As testing is responsible for the product quality
• It is also responsible for the revenue
• Testing represents 50 to 60 of the total
  product cost
• Minimal costs are needed for the required product
  quality
• The costs include the initial and running costs
  of the Automatic Test Equipment (ATE), the costs
  of the DFT , the costs of the BIST, the cost of
  the test development, which is basically CAD
  tools, Test pattern generations, Test
  Programming.

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Terminology

• Fixed Costs (FC) Cost which remain unchanged
  with the production. e.g. Initial costs of the
  ATE, Initial costs of the CAD tools.
• Variable Costs (FC) Costs which increase with
  the production such DFT, BIST, Labor and Energy
  costs.
• Total Costs (TC) They are the sum of the fixed
  and variable costs.
• Average Costs (AC) They are the total costs of
• one produced unit. Obtained by dividing the
  total
• costs by the number of produced units.

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How to control the testing costs?

• 1) We must consider the test complexity
• DFT is important
• What are the measures of Testability?
• Controllability feature which allows controlling
  inputs of
• circuit elements from external ports or
  pins.
• Observability feature which allows observing the
  output of various elements from I/O ports.
• DFT helps
• To reduce test effort
• To reduce test time
• To increase product quality by increasing the
  defects
• coverage

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How to control the testing costs?

• 2) BIST leads to high quality testing as it runs
  at the rate of the
• system speed.
• BIST reduces costs at the production testing
• BIST adds costs at the fabrication and design
• However should one use BIST? Costs against
  benefits must be
• weighted before decision is made.
• 3) Provide high quality testing at each level
  Chip, PCB and sytem level as the rule of ten
  holds.
• What is the rule of ten? If a defect is not
  detected at the chip level, it might cost 10
  times to be detected at the PCB level, the defect
  cost similary at the system level if it has not
  been detected at the PCB level.

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• Thank you
• Questions ?
• Next topic
• Fault Modeling