The SPARC Pipeline

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The SPARC Pipeline

• CS 230
• Dr. McGrew

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von Neumann Cycle ala SPARC

• Instruction Fetch also decodes the instruction
  and obtains any operands from the register file.
• Execute executes arithmetic instruction, and
  computes a branch target address computes the
  memory address for a load or store instruction.

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• Memory Access Accesses memory for a load/store
  instruction fetches the instruction at the
  target address of a branch instruction.
• Store Results Writes the instruction results
  back to the register file.

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Non-Pipelined Execution
Fetch
Exec
Exec
Fetch
Mem
Mem
Write
Write
Pipelined Execution
Fetch
Exec
Mem
Write
Fetch
Exec
Mem
Write
Fetch
Exec
Mem
Write
Fetch
Exec
Mem
Write
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Effect of Load Instruction
Example load o0, o1 add o1, o2,
o2
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The Load Delay Slot
Fetch
Exec
Mem
Write
Load delay slot inserted
Fetch
Exec
Mem
Write
Fetch
Exec
Mem
Write
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Effect of Branch Instruction
Example ble targt add o1, o2, o3
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The Branch Delay Slot
Fetch
Exec
Mem
Write
Branch delay slot instruction
Fetch
Exec
Mem
Write
Fetch
Exec
Mem
Write
Fetch
Exec
Mem
Write