SPARC

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SPARC

• Scalable Processor Architecture

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SPARC

• SPARC is a CPU instruction set architecture
  (ISA), derived from a reduced instruction set
  computer (RISC).
• As an architecture, SPARC allows for a spectrum
  of chip and system implementations at a variety
  of performance points for a range of
  applications, including scientific, programming,
  real-time, and commercial.
• SPARC was designed as a target for optimizing
  compilers and easily pipelined hardware
  implementations.
• SPARC implementations provide exceptionally high
  execution rates and short time-to-market
  development schedules.

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SPARC Processor

• A SPARC processor logically comprises an integer
  unit (IU), a floating-point unit (FPU), and an
  optional coprocessor (CP), each with its own
  registers.
• This organization allows for implementations with
  maximum concurrency between integer,
  floating-point, and coprocessor instruction
  execution. All of the registers, with the
  possible exception of the coprocessors, are 32
  bits wide.
• Instruction operands are generally single
  registers, register pairs, or register
  quadruples.
• The processor can be in either of two modes user
  or supervisor.

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Integer Unit (IU)

• The IU contains registers and controls the
  overall operation of the processor. The IU
  executes the integer arithmetic instructions and
  computes the memory addresses for loads and
  stores.
• It also maintains the program counters and
  controls instruction execution for the FPU and
  the CP.
• An implementation of the IU may contain from 40
  to 520 general-purpose 32-bit registers.

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Floating-point Unit (FPU)

• The FPU has 32 32-bit floating-point registers.
  Thus, the floating-point registers can hold a
  maximum of either 32 single-precision, 16
  double-precision, or 8 quad-precision values.
  Floating-point load/store instructions are used
  to move data between the FPU and memory.

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Coprocessor (CP)

• The instruction set includes support for a
  single, implementation-dependent coprocessor. The
  coprocessor has its own set of registers.
  Coprocessor load/store instructions are used to
  move data between the coprocessor registers and
  memory. For each floating-point load/store in the
  instruction set, there is an analogous
  coprocessor load/store instruction.

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Instructions

• Fall into five basic categories
• Load/store,
• Arithmetic/logical/shift,
• Control transfer,
• Read/write control register
• Floating-point/Coprocessor operate type
  instructions.

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Load/Store Instructions

• Load/store instructions are the only instructions
  that access memory. They use two r registers or
  an r register and a signed 13-bit immediate value
  to calculate a 32-bit, byte-aligned memory
  address.
• The IU appends to this address an address space
  identifier that encodes whether the processor is
  in supervisor or user mode, and that it is a data
  access.
•  

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Arithmetic/Logical/Shift Instructions

• The arithmetic/logical/shift instructions perform
  arithmetic, tagged arithmetic, logical, and shift
  operations. These instructions compute a result
  that is a function of two source operands the
  result is either written into a destination
  register, or discarded.

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Control Transfer Instructions

• Control-transfer instructions (CTIs) include
  PC-relative branches and calls, register-indirect
  jumps, and conditional traps.

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Read/Write Control Register Instructions

• The Read/Write Register instructions read and
  write the contents of software visible
  state/status registers.

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Floating-point/Coprocessor Operate Instructions

• Lastly a floating-point operate (FPop)
  instructions perform all floating-point
  calculations. They are register-to-register
  instructions that operate upon the floating-point
  registers.

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Sources

• http//en.wikipedia.org/wiki/SPARC
• The SPARC Architecture Manual Version 8