332:578 Deep Submicron VLSI Design Lecture 10 Clocking

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332578 Deep SubmicronVLSI DesignLecture
10Clocking

• Michael L. Bushnell -- CAIP Center and WINLAB
• ECE Dept., Rutgers U., Piscataway, NJ

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Outline

• Single-Phase Logic
• Two-Phase Clocking
• Two-Phase Memory
• Four-Phase Memory
• Four-Phase Logic Gates
• Clock Distribution
• Summary

Material from CMOS VLSI Design By Neil E. Weste
and David Harris
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Single-Phase Logic

• For single-phase clocking
• Use n-p zipper CMOS logic with C2MOS latch as O/P
  stage
• Build clk sections resolve when clk 1
• Build clk sections resolve when clk 0

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Single Phase Logicwith n-p Domino CMOS
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n-p Domino CMOS
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Problems of Mixing Logic

• Sometimes mix n-p Domino CMOS with static or
  Domino sections causes problems
• Self-contained sections must have no internal
  races
• Avoid clock skew when different sections are
  cascaded for pipelining

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N-p Logic Design Rules
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n-p Design Rules

• Ensure that clock skew glitches do not propagate
• When using static logic, keep logic static up to
  the C2MOS latch
• For internal races, dynamic logic rules
• Logic blocks must be off during precharge
• During evaluation, internal inputs must make only
  1 transition

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Methods to Avoid Clock Skew
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Two-Phase Clocking

• Single-phase hard to generate distribute 2
  near-perfectly non-overlapping clocks
• Solution generate distribute 2 non-overlapping
  clocks, 1 for Master, 1 for Slave
• Distribute 2 main clocks use local buffers to
  generate local clocks
• For all time, f1 (t) f2 (t) 0
• If f1 is precharge, must be long enough to
  precharge worst circuit node

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Two Phase Clocking
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Two-Phase Memory Structures

• Replicate Single-Phase structures
• f1 feeds master
• f2 feeds slave

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Dynamic Register Structure

• Both types of dynamic register must drive a local
  storage gate

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Reduced Clock Lines

• Use nMOS transmission gates
• Degrade logic 1 to VDD Vtn slows down
  inverter low transition
• Degrades NMH
• Dissipates static power

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Two-Phase Clock Generator
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Clock Distribution

• Globally distribute 2 clocks with / without
  complements
• Distribute 1 clock and generate local 2-phase
  clocks
• Two-phase dynamic domino logic

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Four-Phase Clocking

• Precharge evaluate hold phases
• Simplifies dynamic circuit design
• Historically very popular
• Major problem Multiple clocks use way too much
  power

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Four Phase Memory

• Type 1 4-phase logic
• clk1 0 prechargeclk1 clk2
  1 evaluationclk2 0
  holdclk3 0 Q is prechargedclk3
  clk4 1 conditional evaluation of Q
• Charge sharing can corrupt data

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Type 1 4-Phase Logic
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Type 2 4-Phase Logic
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Four Phase Logic Gate Type A
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Gate Compatibility Rules
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Four Phase Method
clk4
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Type B Four-Phase Logic
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Recommended Clocking Methods

• Single-Phase Clocking
• 1st Time Designs
• Standard Cells
• Gate Arrays
• Two-Phase Clocking
• RAM
• ROM
• PLA

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Clock Distribution

• Total CL on clock may be 1000 pF
• For Trise/fall 1 nsec, Pd 5 Watts
• Use
• A single large buffer (for designs with no
  structured routing) uses too much chip area
• A distributed clock tree (H-tree) (for
  highly-structured DSP chips e.g., FIR filters)

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Solution for Clock Distribution

• H-tree control clock skew (can change metal
  wire delay by changing R by changing wire width)
• H-tree ensures that clock arrives at X points at
  same time
• Wire distance is the same for all paths

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Summary

• Single-Phase Logic
• Two-Phase Clocking
• Two-Phase Memory Gates
• Four-Phase Memory Gates
• Four-Phase Logic Gates
• Clock Distribution