Title: CMS ECAL
1CMS ECAL
- A new readout system architecture for the CMS
ECAL - Magnus Hansen
- 20030930
2Agenda
- Short history
- rEvolution
- A new readout system architecture
- A New ASIC FENIX
- Front End Card
- System Test
- Conclusion
3Agenda
- Short history
- rEvolution
- A new readout system architecture
- A New ASIC FENIX
- Front End Card
- System Test
- Conclusion
New System Architecture
Chips / ASICs
Electronics Modules
System
4Old DesignArchitectural Overview
TTC
TTS
Local Triggers In Stand alone Mode
DAQ Data
Regional Trigger Data
5rEvolution
6New architecture
- Implemented in Front End
- MGPA Multi-ADC for dynamic range compression
and digitization (Change from analogue gain
switching to digital gain selection) - TPG (Trigger Primitive Generator)
- Pipeline storing digitized data waiting for level
1 trigger decision - Primary event buffer
- Implemented in Counting room
- CCS (Clock and Control System card, Collaboration
with CMS Tracker, Pixel) - DCC (Data Concentrator Card)
- TCC (Trigger Concentrator Card)
- SRP (Selective Readout Processor)
7Architectural Overview
TTS
TTC
Local Triggers In Stand alone Mode
Regional Trigger Data
DAQ Data
DAQ Data
Trigger Data
8Front End System Functional Requirements
- Trigger Primitive Generation
- Absolute calibration of each channel
- Implement existing well defined algorithm
- Verification needed before production
- No future basic changes possible
- Latency budget imposed
- Readout of data corresponding to positive trigger
decision - Dead time free
- Three clocks / trigger imposed by TTC system
- 100 kHz level 1 trigger rate
- Some trigger rules apply
- Overflow protection
- Programmable level 1 trigger delay
- Pipeline of programmable length
- Support for monitoring
- Laser monitoring, temperature measurements, etc.
9Other Requirements and Constraints
- Debugging and testability features
- Pattern injection
- Possibility to inject known pattern in the
beginning of the trigger primitive generation and
the readout chain - Boundary scan / scan chains
- BIST
- Built In Self Test for production test and in
situ - Radiation environment
- Size
- Have to fit behind served crystals
- Short development time
- Start June 2002
- Full production January 2004
- One advantage knowledge of the requirements
10The Front End - A Readout Cube
- Motherboard
- Creating flat surface for electronics
installation - Kapton cable to APD connector
- VFE card
- Analogue Signal Processing
- Digitization
- LVR card
- Voltage regulation for FE system
- FE card
- Digital Signal Processing
- Trigger Primitive generation
- Temporary storage
- Pipeline, event buffer
- GOH
- Complete Optical transmitter module including a
GOL and a laser diode
11A technical choice i)
- Single Front End ASIC
- O(500) IOs
- Huge chip
- 20 by 20 mm
- O(4000) chips in CMS ECAL
- Quickly considered as a non-optimal choice
12A technical choice ii)
- Seven Front End ASICs
- Three types
- O(150) IOs each
- 7 by 7 mm
- O(20000) O(4000) O(4000) chips in CMS ECAL
- Soon considered as a non-optimal choice
13The technical choice
- Seven Front End ASICs
- Single type
- Three operation modes
- O(150) IOs
- 7 by 7 mm
- O(30000) chips in CMS ECAL
- Considered as an optimal choice
- The new ASIC is called FENIX
- Front End New Intermediate data eXtractor
14FENIXDescription 1 Four Operation Modes
- Strip
- Creating filtered Strip / Pseudo-strip sums for
TCP inputs - Pipelines and primary event buffers
- TCP
- Trigger Cell Processor
- Finalising the trigger primitive for one trigger
tower in the Barrel - DAQ
- Tower (Super Crystal) readout state machine
- Event encapsulation
- MEM
- Reading out the Laser monitoring monitoring
system - Pipelines and primary event buffers
15FENIXDescription 2 Control
- Fast control
- T1 signal as defined in the Tracker slow control
system - 100 gt Level 1 Trigger accept
- 101 gt BC0
- Local Bunch Crossing counter reset
- 110 gt Re-synch
- Reset of all counters and state machines
- 111 gt Force VFE mode
- From programmable default mode to programmable
calibration mode - 110110 gt Power-up reset
- Reset of all counters and state machines and load
default values into all registers - 1100110 gt Power-up reset
- As above
- Slow Control
- I2C interface
- Extended 10 bit addressing
- Standard protocol
- Direct addressing of all set-up addresses
- Compatible with CCU I2C master ports
- Fully synchronous design
- Synthesizable
- Auto PR
- 150 set-up addresses
- 132 Set-up registers
- 18 RAM access
16Development Acceleration
- Intermediate device
- Xilinx FPGA
- Cadence for simulation
- Synplify for synthesis
- Modern ASIC design tools
- Synopsis for synthesis
- Silicon Ensemble for Place Route
- Very short design turn-around time
- 2 weeks claimed
- Generic HDL description
- No component instantiation
17ASIC Emulation in FPGA
- Features
- Observable functionality identical
- Identical footprint
- Identical pin-out
- Not implemented to save resources
- Triple-redundancy in registers
- Error Correcting Code in RAMs
- BIST in RAMs
18ASIC Emulation in FPGA- Applied HDL design rules
- Generic Source Code
- No process dependent component instantiation
- Exception RAM
- Technology specific, recommended not to infer
- Adopted strategy
- All functional simulation done with generic RAM
- Superset of Xilinx RAM and ASIC RAM used
- For the FPGA, the Xilinx RAM block is wrapped and
instantiated - Routed design simulated and verified for
conformity - For the ASIC, the modular static RAM cell
developed at CERN is wrapped and instantiated - Routed design simulated and verified for
conformity
19FENIX ASICRadiation Tolerance Strategy
- Observation
- ASIC technology is radiation tolerant
- Registers and RAM cells subject to SEU
- Strategy
- Protect against SEU
- Not protect against hardware failure
- Testability
- Always a challenge
- Improved by insertion of a testability flag
20FENIX ASIC SEU Tolerance 1 Set-up Registers
- Set-up registers
- Triple-redundant flip-flops
- SEU resistant
- Voting logic
- three (two) clocks long write pulse needed
- Features
- Synthesizable
- Test
- Any discrepancy flagged
- Discrepancy when written
21Triple-redundantSet-up registerVHDL code
setup_register process (clock40) begin
if rising_edge(clock40)then if
pwup_reset '0' then register1_8b lt
pwup_value seu_flag lt '0' elsif
address register_address and write_enable '1'
then register1_8b lt write_data
else register1_8b lt
voted_register_value_8b end if
register3_8b lt register2_8b
register2_8b lt register1_8b if
register1_8b register2_8b and register1_8b
register3_8b then seu_flag lt '0'
else seu_flag lt '1' end
if else null end if end
process setup_register
22FENIX ASIC SEU Tolerance 2 State Machine
- State Machine
- Triple-redundant
- SEU resistant
- Voting logic
- Except state changes
- Features
- Synthesizable
- Test
- Any discrepancy flagged
- Discrepancy when state change
23FENIX ASICSEU Tolerance 3 RAM
- RAM
- Hamming code
- Encode at write
- Decode Correct at read
- one bit error correction
- Features
- Synthesizable
- Single bit SEU safe
- Test
- ECC Decoder
- During BIST execution
- ECC Encoder
- During normal operation
- Through slow control (I2C)
24FENIX ASICTestability
- Test time budget 1 second
- Without chip handling
- Triple-redundant Registers
- Testability flag can be used as a signature of
operation
- RAM BIST
- Fully automatic
- Write whole RAM and read back
- Launched by a pulse on IO pin
- Boundary scan
- Tester
- Observable on external pins
- Boundary scan
- Tester
- Can be launched and monitored in situ (I2C)
25FENIX ASICStatus and Plans
- First submitted February 2003
- Received back from foundry in May
- Not yet received back from packaging
- Becoming critical
- Next submission after ESR
- 9th of October
- Engineering run
- Final design
- O(3000) dies, for up to 3 CMS ECAL Super Modules
- Tested chips back before end 2003
- Production
- Beginning of 2004
26FE CardFunctionality and Performance
- Full TPG in Barrel
- Sum of Five filtered strip sums
- Single data link to TCC and regional trigger
- 11 clocks latency
- FE card input to GOH connector
- Partial TPG in End Cap
- Five filtered strip sums
- Five data links to TCC and regional trigger
- 7 clocks latency
- FE card input to GOH connector
- Readout
- Serves 25 channels
- Single data link to DCC and DAQ
- Dead time free
- 7.2us service time, 25 primary event buffers, (10
samp/ch/evt, P(nd) 10-8) - Null event insertion up to 127 pending events
- Programmable pipeline length corresponding to
level 1 trigger delay
TTS for CMS DAQ, A. Racz
27FE card Layout
28Tower in Super Module
Trigger GOH
QPLL
VFE
CCU
Readout GOH
FENIX FPGA
LVR
29Beam Test 2003
30Conclusion
- A New Readout System Architecture for CMS ECAL
has been presented - The CMS ECAL Front End Card
- Serving 25 readout channels
- Tower in the Barrel
- Super-Crystal in the End Cap
- The FENIX chip
- Implements the main functionality on the Front
End card - Three (four) operation modes
- FPGA emulator implemented
- ASIC prototype implemented, Final design
submitted after ESR - Prototype system successfully tested in beam