MultiBit Memory

1
Multi-Bit Memory

• Lecture 05

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D-type Latch
Implement this circuit in a Spartan 2
FPGA. Notice that the synthesis tool inferred a
latch and produced a warning. Sometimes latches
are inferred by accident. In this case we created
the latch intentionally.
entity example2 is Port ( D, C in
STD_LOGIC Q, Qbar out STD_LOGIC) end entity
example2 architecture dataflow of example2
is signal fb std_logic begin fb lt fb when
( C '0' ) else D when ( C '1'
) Q lt fb Qbar lt not fb end architecture
dataflow
Try rewriting the conditional assignment.
A transparent latch is like a video camera with a
pause button.
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D-type Flip-Flop
entity example3 is Port ( C, D in
STD_LOGIC Q, Qbar out
STD_LOGIC) end entity example3 architecture
dataflow of example3 is signal fb
std_logic begin fb lt D when ( C '1' and
C'Event ) else fb Q lt fb Qbar lt not fb end
architecture dataflow
Implement this circuit in a Spartan 2
FPGA. Notice that the synthesis tool decided use
TWO flip-flops.
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Signal Attributes
VHDL has a few built-in functions (called signal
attributes) that are very useful. These functions
are so common that the syntax for calling the
function is unusual but convenient.
Cevent is a function that takes a signal called
C as its input and returns a BOOLEAN value as
its output. At each step of simulation time
Cevent is true if C changed value or false if C
remained the same.
The previous example uses event to demonstrate
modeling an edge-sensitive input.
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Statement Sensitivity Lists
VHDL is designed to construct models of DIGITAL
systems. VHDL models can be used TWO ways, 1) to
run simulations, and 2) to synthesize circuits.
A simulator begins a run at time0 and sweeps
forward in steps. The size of each step is a
constant called the simulation step time. I
usually set this to be 1 nanoSecond. At each step
the simulator must evaluate the state of the
system. The simulators that read VHDL models are
called discrete-event simulators because they
recognize that they only need to reevaluate the
state of the system if a change has occurred.
(Event)
Each signal assignment has a sensitivity list.
This is a list of signals that appear on the
right-hand side of the assignment. The assignment
is only evaluated if an event occurs on a signal
in its sensitivity list.
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Monitoring Transactions
VHDL has a signal attribute for monitoring
transaction as they expire.
transaction is a built-in function that takes a
signal as its input argument and returns a
signal of type boolean. The returned signal
toggles every time a transaction expires on the
input signals driver.
architecture waveforms of example4 is signal C,
W std_logic '0' signal probe
bit begin C lt not C after 20 ns W lt C, not
C after 2 ns, C after 4 ns, not C after 6 ns, C
after 8 ns, C after 10 ns probe lt
W'transaction end architecture waveforms
Notice that some transactions do NOT cause events
when they expire.
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Transactions in the D-type Flip-flop
architecture dataflow of example5 is signal fb
std_logic signal probe bit begin fb lt D
when ( C '1' and C'Event ) else fb probe lt
fb'transaction Q lt fb Qbar lt not fb end
architecture dataflow
Notice that transactions are expiring due to both
C, D and fb. An strange situation occurs whenever
fb changes.
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Process Statements
A process is a block that represent a single
concurrent statement. Many sequential statements
can be encapsulated by a process. Sequential
statements operate similarly to the statements in
a programming language. Note that a process
executes instantaneously when considering
simulation time.
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Process Statements
Processes are used to construct behavioural
models.
Let us assume that every process has been written
with a sensitivity list. Every process will
execute at time0 and then enter a state of
suspension until an event occurs on any signal in
its sensitivity list. The process will execute
in every time step that contains such an event.
Processes can also be written without the
sensitivity list. In this case the process MUST
contain a WAIT statement. We will discuss this
method later.
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D-type Flip-Flop
architecture Behavioral of example7 is
signal stateA, stateB std_logic begin Q
lt stateA Qbar lt not stateA
Dff process ( C ) begin
if ( C '1' ) then stateA lt
D stateB lt D'delayed(1
ns) end if end process
Dff end architecture Behavioral
Notice that I have used delayed() to resolve the
problem that we discussed earlier.
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Registers
We can store multi-bit numbers in a memory cell
called a register. A register is simply a group
of flip-flops with a single common clock.
Notice that the circuit symbol for a register
looks exactly the same as the symbol for a D-type
flip-flop. We know that the symbol represents a
register because of the fact that there are 8
D-inputs and 8 Q-outputs.
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Registers in VHDL
entity example1 is Port ( En, Clk in
STD_LOGIC D in std_logic_vector(7 downto 0)
Q out STD_LOGIC_vector(7 downto 0)
) end entity example1 architecture Behavioral
of example1 is begin R1 process ( clk
) begin if ( rising_edge(clk) ) then
if En '1' then Q lt D end
if end if end process R1 end
Behavioral
Notice that everything looks the same as a D-type
flip-flop except for the statements typed in RED.
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Arrays in VHDL
An array is a composite data-type that groups
elements of a specified type. A signal can be
declared to have values that are arrays. We can
make reference to the individual elements of an
array by indexing. The most common method of
indexing an array involves using an integer to
specify the index.

• An array-type must first be declared before the
  array-type can be used in the declaration of a
  signal. The array-type declaration must specify 3
  pieces of information.
• The name of the array-type.
• The allowable range used for indexing the array.
• The data-type used for the elements of the array.

type coordinate is array ( 1 to 3 ) of real --
array-type declaration signal WhereAmI
coordinate -- signal declaration
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Unconstrained Array Declarations
It is also possible to omit the index constraint
when declaring the array-type. This form of
declaration results in an incomplete data-type
and thus the missing piece of information MUST be
provided when the unconstrained array-type is
used to declare a signal.
type coordinate is array ( integer range ltgt ) of
real signal WhereOnPlane coordinate( 1 to 2
) signal WhereInSpace coordinate( 1 to 3 )
The package ieee.std_logic defines an
unconstrained array-type called
std_logic_vector. We must provide the index range
specification when declaring signals. signal Din
std_logic_vector( 7 downto 0 ) signal Qout
std_logic_vector( 1 to 8 )
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Array Access
The following example demonstrates how individual
elements of array-type signals can be referenced
when forming expressions.
signal a, b std_logic_vector( 7 downto 0
) a(3) lt b(5) a(4 downto 2) lt b(7 downto 5)
Notice that a contiguous group of array elements
can be referenced in a single expression. A
contiguous group of elements is called an array
slice.
Array slices can also be formed using a
concatenation operator, .
a(6 downto 3) lt 1 b(4 downto 2) a(7 downto
0) lt a(3 downto 0) b(3 downto 0)
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Array Initialization
You will often need to assign constant values to
array-type signals. There are a few different
ways to form constants or array-type expressions.
The most fundamental method of forming an array
expression uses ( , , ) called an array
aggregate. a(6 downto 1) lt ('1','0','X','0','0',
'X') ( a(3), a(6) ) lt b(3 downto 2) a(7
downto 0) lt ( 1 gt 'X', 3 to 4 gt 'U', others gt
b(2) )
If the element types are simple
character_literals we can form array constants by
enclosing the values with . a(6 downto 1)
lt "10X001"