Chapter 3 Arithmetic for Computers

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Chapter 3Arithmetic for Computers
Computer Organization

• Kevin Schaffer
• Department of Computer Science
• Hiram College

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Combinational vs. Sequential

• Combinational logic has no memory, outputs depend
  entirely on inputs
• Sequential logic has memory, outputs depend on
  both inputs and the current contents of memory
• Memory in sequential logic is called state

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Combinational Logic

• Truth tables
• Logic equations
• Gates

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Truth Tables

• Gives values of outputs for each combination of
  inputs
• Logic block with n inputs is defined by a truth
  table with 2n entries

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Logic Equations

• OR (Logical sum) A B
• AND (Logical product) A B
• NOT (Logical complement) A'

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Boolean Algebra

• Identity laws
• A 0 A
• A 1 A
• Zero and One laws
• A 1 1
• A 0 0
• Inverse laws
• A A' 1
• A A' 0

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Boolean Algebra (cont'd)

• Commutative laws
• A B B A
• A B B A
• Associative laws
• A (B C) (A B) C
• A (B C) (A B) C
• Distributive laws
• A (B C) (A B) (A C)
• A (B C) (A B) (A C)

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Gates

• AND gate
• OR gate
• Inverter (NOT gate)

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Inversion Bubbles

• Inverters are so commonly used that designers
  have developed a shorthand notation
• Instead of using explicit inverters, you can
  attach bubbles to the inputs or outputs of other
  gates

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Universal Gates

• Any combinational function can be built from AND,
  OR and NOT gates
• However, there are universal gates that alone can
  implement any function
• NAND and NOR are two such gates
• NAND and NOR are AND and OR gates with inverted
  outputs

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Decoder

• A decoder asserts exactly one of its 2n outputs
  for each combination of its n inputs
• The n inputs are interpreted as an n-bit binary
  number

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Decoder (cont'd)
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Multiplexor

• A multiplexor selects one of its 2n data inputs,
  based on the value of its n selector inputs, to
  become its output
• The n selector inputs are interpreted as an n-bit
  binary number

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Two-Level Logic

• Any combinational function can be expressed in a
  canonical two-level representation
• Sum of products is a logical sum (OR) of logical
  products (AND)
• Product of sums is just the opposite

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Sum of Products
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PLAs
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PLAs (cont'd)
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Arrays of Logic Elements
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Number Systems

• Decimal (base 10)
• 1234567890ten
• Hexadecimal (base 16)
• 499602D2hex
• Binary (base 2)
• 1001001100101100000001011010010two

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Data Types

• Integers
• Unsigned integers
• Signed integers
• Real numbers
• Floating-point numbers
• Fixed-point numbers
• Strings

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Unsigned Integers

• Each bit bi has value bi 2i
• Count from right to left starting at zero
• Leftmost is most significant bit (MSB)
• Rightmost is least significant bit (LSB)
• To convert from binary to decimal, sum those
  values together
• Repeated division by two can convert decimal to
  binary the remainders form the binary number
  from right to left

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Unsigned Integers

• At least lg n bits are required to represent an
  integer n
• With k bits you can represent integers from 0 to
  2k 1

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Signed Integers

• Many ways to encode signed integers
• Signed-magnitude
• Biased
• One's complement
• Two's complement
• In practice, two's complement is the most
  commonly used

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Signed-Magnitude

• Explicit sign bit
• Remaining bits encode unsigned magnitude
• Two representations for zero (0 and -0)
• Addition and subtraction are more complicated

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Biased

• Add a bias to the signed number in order to make
  it unsigned
• Subtract the bias to return the original value
• Typically the bias is 2k-1 for a k-bit
  representation

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Two's Complement

• Most significant bit has a negative weight
• To negate invert bits and add one
• Implicit sign bit
• One negative number that has no positive
• Handles overflow well

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Zero/Sign Extension

• Extension takes a number represented in m bits
  and converts it to n bits (m lt n) while
  preserving its value
• For unsigned numbers just add zeros to the left
  (zero extension)
• For two's complement signed numbers, replicate
  the sign bit (sign extension)

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Addition

• Similar to long-hand addition in decimal
• Start at right and move left
• A carry out of the ith bit is added to the (i
  1)th bit
• Two's complement addition is the same as unsigned
  addition, except that you must ignore a carry out
  of the MSB
• To subtract just negate the second operand

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Overflow

• Overflow occurs when the correct result cannot be
  represented
• An unsigned addition overflows if there is a
  carry out of the most significant bit
• In two's complement signed addition, overflow
  occurs when
• Sum of positive numbers is negative
• Sum of negative numbers is positive
• If the signs differ then overflow cannot occur

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Overflow in MIPS

• In MIPS there are two versions of each add and
  subtract instruction
• Add (add), add immediate (addi), and subtract
  (sub) cause an exception on overflow
• Add unsigned (addu), add immediate unsigned
  (addiu), and subtract unsigned (subu) ignore
  overflow
• C code always uses the unsigned versions because
  it ignores overflow

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Addition in Hardware

• A full adder takes two inputs bits and a carry in
  and produces a sum bit and a carry out
• If we connect carry outs and carry ins then we
  can add multi-bit values
• This is a ripple-carry adder
• Ripple-carry adders are the simplest and the
  slowest types of adders

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Full Adder
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ALU

• Arithmetic/logic unit
• Computes an arithmetic, logic, or comparison
  operation between two operands
• Also generates a set of condition codes

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Building an ALU

• To build the 32-bit ALU needed for MIPS, start
  with a 1-bit ALU and then connect 32 of them
  together
• ALU implements add, sub, and, or, nor, and slt
• It must also be able to test for equality so we
  can implement beq

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1-bit ALU

• This 1-bit logic unit can compute the AND or OR
  of 2 bits
• Both the AND and the OR are computed in parallel
• The multiplexor chooses the result based on the
  operation

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ALU with Addition

• With a full adder, the ALU can perform addition
• This requires a carry input and carry output for
  the 1-bit ALU

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Combining 1-bit ALUs

• To create a 32-bit ALU we must connect the carry
  inputs and outputs of the 1-bit ALUs in
  ripple-carry fashion
• The same operation is distributed to all 1-bit
  ALUs

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Subtraction

• Subtraction is implemented by negating the second
  operand before addition
• To negate a number in two's complement, invert
  the bits and add one
• a b a (b) a (b 1) a b 1
• We can take advantage of the carry in to the LSB
  in order to add one to result

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ALU with Subtraction
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NOR

• We take advantage of DeMorgan's laws to implement
  NOR with existing hardware
• (A B)' A' B'
• Already have hardware to invert B, add hardware
  to also invert A

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Set on Less Than

• Set on less than (slt) compares its operands and
  produces a result of 1 if a lt b or 0 otherwise
• To do the comparison, perform a subtraction
• If a lt b, the result will be negative
• Just send the MSB of the subtraction result to
  the LSB of the ALU result
• All other result bits will be 0s

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ALU with Set on Less Than

• Result multiplexor has been expanded to pass
  through the Less input
• For all ALUs except the LSB one, Less will be 0
• For LSB ALU, Less will be comparison result (from
  MSB ALU)

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MSB ALU

• The MSB ALU has an additional output (Set) for
  the comparison result
• Set will be connected to the Less input of the
  LSB ALU

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Putting it Together
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Testing for Equality

• ALU also performs the test for equality for the
  branch if equal (beq) instruction
• To test for equality, subtract the operands and
  check if the result is zero

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ALU with Condition Codes
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Complete ALU
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Delay in Ripple Carry Adders

• Ripple carry adders are simple, but slow
• The critical path (longest path any signal takes)
  goes through all the full adders
• Therefore the delay is O(k) for a k-bit adder

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Two-Level Carry Logic

• Any combinational logic function can be expressed
  in sum of products form
• Formula for carry logic
• c1 (b0 c0) (a0 c0) (a0 b0)
• c2 (b1 c1) (a1 c1) (a1 b1)
• Substituting and rewriting yields
• c2 (a1 a0 b0) (a1 a0 c0) (a1 b0
  c0) (b1 a0 b0) (b1 a0 c0) (b1 b0
  c0) (a1 b1)

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Carry Lookahead

• Two-level carry logic is fast but impractical
• The amount of hardware necessary grows rapidly
  with the number of bits
• A carry-lookahead adder uses multiple levels of
  carry logic to limit complexity

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Simplifying the Carry Logic

• Factor the original carry equation
• ci1 (ai bi) (ai bi) ci
• Rewrite c2 using this formula
• c2 (a1 b1) (a1 b1) ((a0 b0) (a0
  b0) c0)
• Note the repeated appearance of the generate (gi)
  and propagate (pi) terms
• gi ai bi
• pi ai bi

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Generate and Propagate

• We can rewrite the carry equation as
• ci1 gi (pi ci)
• An adder will produce a carry out if
• It generates a carry
• It propagates a carry, and there was a carry in

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Example 4-bit Adder

• Carry lookahead logic for a 4-bit adder
• c1 g0 (p0 c0)
• c2 g1 (p1 g0) (p1 p0 c0)
• c3 g2 (p2 g1) (p2 p1 g0) (p2 p1
  p0 c0)
• c4 g3 (p3 g2) (p3 p2 g1) (p3 p2
  p1 g0) (p3 p2 p1 p0 c0)
• Even this simplified logic becomes complex
  quickly for large adders

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Making Larger Adders

• We can use the 4-bit adder as a building block to
  make larger adders
• If we chain the carries from the 4-bit adders in
  ripple carry fashion, it will be faster than a
  pure ripple carry adder
• Can we do better?

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Multi-Level Carry Lookahead

• The complexity of the carry prediction logic can
  be limited by using a hierarchical organization
• This leads to a delay of O(lg k) for a k-bit adder

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Group Propagate

• Group propagate signals for 4-bit adders
• P0 p3 p2 p1 p0
• P1 p7 p6 p5 p4
• P2 p11 p10 p9 p8
• P3 p15 p14 p13 p12
• Pi is true if all the bits in the group will
  propagate a carry

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Group Generate

• Group generate signals for 4-bit adders
• G0 g3 (p3 g2) (p3 p2 g1) (p3 p2 p1
  g0)
• G1 g7 (p7 g6) (p7 p6 g5) (p7 p6 p5
  g4)
• G2 g11 (p11 g10) (p11 p10 g9) (p11
  p10 p9 g8)
• G3 g15 (p15 g14) (p15 p14 g13) (p15
  p14 p13 g12)
• Gi is true if a group always generates a carry

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Clocks

• A clock is a logic signal that oscillates
  between0 and 1 with a fixed frequency
• When the clock transitions from 0 to 1, this is
  called a rising (or positive) edge a transition
  from 1 to 0 is a falling (or negative) edge
• Logic can be built to respond to the value of the
  clock (level-sensitive) or to its edges
  (edge-sensitive)

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Clocks

• Clock period (or clock cycle time) is the inverse
  of the clock frequency
• Example a clock with a period of 500 ps has a
  frequency of 2 GHz

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Latches

• Latches are level-sensitive storage elements
• The simplest type of latch is the S-R latch
  (set-reset latch)
• Q is the currently stored value

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Clocked Latches

• A D latch (data latch) is an example of a clocked
  latch
• When the clock (C) is high, the data input (D) is
  copied to the output
• When the clock is low, the output remains
  unchanged

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Latch Example
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Flip-Flops

• Flip-flops are edge-sensitive store elements
• A D flip-flop updates its stored value only on a
  rising (or falling) clock edge
• A register consists of multiple D flip-flops with
  a common clock

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Flip-Flop Example
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Setup and Hold Time

• Inputs must be stable before (setup time) and
  after (hold time) the clock edge
• Failure to meet setup and hold time requirements
  may result in unpredictable behavior

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Mixed Logic 1

• Data from state element 1 propagates through the
  combinational logic
• At the clock edge, the output is sampled and
  stored into state element 2

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Mixed Logic 2

• With edge-sensitive clocking, it's possible to
  write back into the same state element

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Register Files

• Array of registers
• Multiple ports allow multiple simultaneous reads
  and writes
• Used to implement general-purpose registers in
  MIPS

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Register File Read Ports
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Register File Write Port
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Multiplication

• Just like long-hand multiplication in decimal
• Take the digits of the multiplier from right to
  left and multiply each one by the multiplicand
• Each partial product is shifted left one place
  more than the previous one
• Add together all the partial products
• Multiplication of two k-bit numbers may result in
  a 2k-bit product

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Multiplication (cont'd)

• In binary it is simple to generate the partial
  products
• Thus the difficultly in multiplication is adding
  the partial products

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Shift-Add Multiplier 1
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Multiplication Algorithm 1

• Repeat the following steps 32 times
• If Multiplier0 is 1 then add multiplicand to
  product and place the result in Product register
• Shift the Multiplicand register left 1 bit
• Shift the Multiplier register right 1 bit

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Shift-Add Multiplier 2
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Multiplication Algorithm 2

• Repeat the following steps 32 times
• If Product0 is 1 then add multiplicand to the
  left half of the product and place the result in
  the left half of the Product register
• Shift the Product register right 1 bit

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Parallel Multipliers

• Parallel multipliers trade additional hardware
  for faster multiplication
• A carry save adder reduces a sum of three
  operands to a sum of two operands
• Multiple levels of carry save adders combined
  with a final normal adder can add multiple
  operands in logarithmic time

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Tree of Adders
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Tree of Carry Save Adders
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Division

• Once again we go back to the long-hand decimal
  algorithm to understand the binary algorithm
• The dividend is divided by the divisor which
  produces a quotient and a remainder

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Shift-Subtract Divider 1
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Division Algorithm 1

• Repeat the following steps 33 times
• Subtract the Divisor register from the Remainder
  register and place the result in the Remainder
  register
• If Remainder is greater than or equal to zero
  then shift the Quotient left and insert a 1
• If Remainder is less than zero then add the
  Divisor back to the Remainder also shift the
  Quotient left and insert a 0
• Shift the Divisor register right 1 bit

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Shift-Subtract Divider 2
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Real Numbers

• There are too many real numbers to represent
  accurately in a computer
• Instead we use approximations to real numbers
• Fixed-point numbers split a number to a whole
  part and a fractional part (radix point is fixed)
• Does not require special hardware
• Floating-point numbers allow the radix point to
  move by encoding its position explicitly
• More flexible

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Binary Floating-Point

• Conversion from decimal to binary
• Use repeated division for the whole part
• Use repeated multiplication for the fraction
• From binary to decimal
• Multiply each bit by its weight
• Bits after the decimal point are 2-1, 2-2, etc.
• Normalization ensures that there is exactly one
  bit to the left of the decimal point
• Results in a unique representation for every
  number

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Floating-Point Formats

• In the past each architecture had its own
  floating-point format
• This made it difficult to exchange data
• Today virtually all computers use the IEEE
  floating-point standard
• Sometimes non-standard formats are used for extra
  precision
• Sometimes only parts of the standard are
  implemented in order to improve performance

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IEEE Floating-Point Standard

• Format
• Sign bit
• Exponent (biased)
• Fraction (with a hidden bit)
• Two sizes
• Single-precision has an 8-bit exponent and 23-bit
  fraction (32-bit total) bias is 127
• Double-precision has an 11-bit exponent and a
  52-bit fraction (64-bit total) bias is 1023

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IEEE FP Numbers

• The value of a normal number is (-1)s 1.f 2e
• s is the sign bit
• f is the fraction
• e is the unbiased exponent
• The 1 in front of the fraction is the hidden bit
  the 1.f term is called the significand
• Note that the sign bit determines the sign of the
  number as a whole the exponent has its own sign

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Special Numbers

• IEEE FP also defines classes of special numbers
• Denormalized numbers
• Zero
• Infinity
• Not a Number (NaN)

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Zero

• All normalized FP numbers have a 1 before the
  radix point, this makes it impossible to exactly
  represent zero
• IEEE uses a special encoding for zero
• Biased exponent is zero
• Fraction is zero
• Due to the signed-magnitude representation, there
  is both a positive and negative zero

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Denormalized Numbers

• It is also difficult to represent numbers that
  are close to zero in normalized form
• Denormalized numbers are stored unnormalized and
  therefore do not have a hidden bit
• IEEE also uses a special encoding for denormals
• Biased exponent is zero
• Fraction is not zero
• Denormals help prevent underflow
• Also known as subnormal numbers

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Underflow

• Underflow occurs when a number is too small in
  magnitude to be represented
• This occurs when the exponent is less than the
  minimum representable value
• Be careful not to confuse negative overflow with
  underflow
• Underflow is unique to floating-point integer
  arithmetic can never underflow

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Infinity

• IEEE has an encoding for infinity
• Biased exponent is maximum (255 for single)
• Fraction is zero
• Sign determines positive or negative infinity
• Infinities result from overflow or division of a
  non-zero by zero
• Arithmetic with infinities is supported where it
  makes sense, eg x 8 8

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Not a Number (NaN)

• In IEEE an undefined operation results in a
  special value called Not a Number (NaN)
• Biased exponent is maximum (255 for single)
• Fraction is not zero
• Sign is ignored
• Example of undefined operations
• Dividing zero by zero
• Adding infinities of different signs
• Square root of a negative number
• Any operation on a NaN results in a NaN

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Types of Numbers in IEEE
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Conversion to IEEE FP

• Convert decimal real number to binary
• Repeated division for the integer part
• Repeated multiplication for the fractional part
• Normalize the binary real number
• Move the radix point left, increase exponent
• Move the radix point right, decrease exponent
• Add bias to exponent and convert to binary
• Remove hidden bit from significand
• Determine sign

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Conversion from IEEE FP

• Add hidden bit to fraction
• Convert exponent to a decimal number
• Subtract bias from exponent
• Unnormalize significand
• Convert significand to decimal by multiplying
  bits by their weights
• Negate if sign bit is a 1

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Floating-Point Addition

• Adjust radix point of smaller number so it is
  aligned with larger number
• Add the significands
• Normalize
• Round

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Floating-Point Multiplication

• Add the exponents and subtract the bias
• Multiply the significands
• Normalize
• Round
• Compare signs

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Floating-Point in MIPS

• Floating-point numbers are stored in a separate
  set of registers (f0..f31)
• Double-precision numbers use pairs of registers
• Arithmetic instructions
• add.f, sub.f, mul.f, div.f
• abs.f, mov.f, neg.f
• c.eq.f, c.lt.f, ...
• f is s for single-precision or d or
  double-precision

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Verilog

• Hardware description language (HDL)
• Similar to a programming language, but describes
  hardware instead of software
• Used for both simulation and synthesis
• Syntax borrows from C

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Modules

• Design is composed of modules
• Modules connect to other modules through input
  and output ports
• A behavioral specification describes the
  operation of a module functionally
• A structural specification describes a module as
  a collection of other modules

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Defining a Module

• module example(a, b, result)
• input a, b
• output result
• assign result a b
• endmodule

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Data Types

• A wire always specifies combinational logic
• A reg (register) can specify either combinational
  or sequential logic
• Multi-bit signals are declared as arrays
• wire 310 X
• Use an array of registers to describe a register
  file or a memory
• reg 310 registerfile031

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Constants

• Logic values 0, 1, x (unknown), or z (tristate)
• Specify constants as size ' base digits
• Examples
• Binary 4'b1010
• Hexadecimal 8'hFF
• Decimal 5'd31

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Concatenation

• Concatenate bit strings together by placing them
  in curly braces
• A3116, B150
• Replicate bit strings by placing a repetition
  count in front of the braces
• 162'b01

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Operators

• Logical operators AND (), OR (), NOT ()
• Apply to individual bits or multi-bit values
• Arithmetic operators add () and subtract ()
• Apply to multi-bit values
• Treat operands as unsigned integers
• Shift operators left shift (ltlt) and right shift
  (gtgt)
• Apply to multi-bit values

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Continuous Assignment

• assign wire expression
• Assigns a value to a wire, when the value of the
  expression changes the value of the wire also
  changes
• Example assign F (A B) C
• All assignments are done concurrently

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Always Blocks

• Syntax
• always _at_(sensitivity list)begin bodyend
• Executes statements in the body whenever a signal
  in the sensitivity list changes
• Only regs can be assigned in an always block

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Always Blocks (cont'd)

• Example
• always _at_(A or B or C)begin F lt (A B)
  Cend
• Use of non-blocking assignment operator (lt)
  indicates that assignments are done concurrently

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If Statements

• Example (2 to 1 multiplexor)
• always _at_(a or b or sel)begin if (sel 0)
  result lt a else result lt bend

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Case Statements

• Example (4 to 1 multiplexor)
• always _at_(a or b or c or d or sel)begin case
  (sel) 0 result lt a 1 result lt b
  2 result lt c 3 result lt d default
  result lt 1'bx endcaseend