Silicon Tracker Electronics for the Linear Collider

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Silicon Tracker Electronics for the Linear
Collider
Aurore Savoy-Navarro, LPNHE-Université
de Paris 6/CNRS-IN2P3,
on behalf of Jean
François Genat, Hervé Lebbolo, Philippe Bailly,
Aurore Savoy-Navarro
ALCPG Workshop, Victoria (British Columbia)
July 28th to 31st 2004.
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Context
A Silicon Strip Tracker a few 100m2, a few 106
channels to read Asynchronous events
1 ms Data taking/pre-processing
200 ms (could also be adapted for the
warm machine) Occupancy
a few Collaborative effort This report
focuses on what is being developed in Europe,
within the SiLC Collaboration. It is important
to note that we are also in close contact with
what is being done at SCIPP-Santa Cruz (see
Bruce Schumms talk DOE proposal
submitted by SCIPP-UCSC, SLAC LPNHE-Paris). In
particular both teams intend to exchange chips
test procedures when each developed chip will
come back from foundry.
A. Savoy-Navarro, SiLC-Electronics, Victoria,
July 04
3
RD on F.E readout for long ladders

• New V.A. IDEAS chip adapted to LC Si-tracking
  (IDEAS Vienna Karlsruhe)
• Work in progress on a new F.E.E. _at_ LPNHE-Paris
  (collaboration underway
• with other labs)

Goals Low noise preamplifier Long shaping
time Very low power dissipation Shared
ADC/TDC Digitization _at_ sparsification Power
cycling Compact and transparent Choice of DSµE
A.Savoy-Navarro,SiLC Electronics, Victoria, July
04
4
Data Charge 1-45 MIP, Time 1ns
(To Trigger)
Silicon Strip 50 -100 pF

PA shaper, Peak 2xDisc
ADC
Ch
Time
Storage
Time, Charge
Counter
Readout (From Trigger)
Technology Deep Sub-Micron CMOS UMC 0.18 mm

A.Savoy-Navarro, SiLC-Electronics, Victoria, July
04
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Analog section
N.B The time measurement will not be included in
the first FE design. It will be first experienced
on the Lab test bench.
Charge Preamp Cf 400 fF
CR-RC Shaper
Sample and Hold
Charge
input
Hold
High threshold
Time
Digital delay
Low threshold
Aurore Savoy-Navarro, SiLC Electronics, Victoria
July 04.
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Preamp schematic
A. Savoy-Navarro, SiLC Electronics, Victoria,
July 04.
7
Overall Readout design
SH digitization
Amplification long shaping storage time
tagging
Analog pipeline or not and sparsification
A/D Wilkinson type, highly shared (128 or
256)
A. Savoy-Navarro, SiLC Electronics, Victoria,
July 04
8
ADC simulations
Conversion time of 4 µs, 10 bits and 500 MHz
(internal clock)
A. Savoy-Navarro, SiLC Electronics, Victoria,
July 04
9
Deep Sub-Micron CMOS 0.18 mm technology
Preamp - Shaper - 1-45 MIP - Gain 8
mV/MIP - 195 mW/ch If 100 MIPS
needed, just twice Preamp power
Timing

• 60 mW
• Two-threshold discriminator

ADC
- 4 ms
conversion time
- 10
bits (500 MHz internal clock)
- 40
mW/ch

A. Savoy-Navarro, SiLC Electronics, Victoria,
July 04
10
Performance
- Noise Preamp Shaper _at_ 5 ms
shaping time, 50 pF detector (no leak, no bias
resistor) 690 e- ENC S/N 40 Gain
8mV/MIP - Power - Preamp Shaper
timing Preamp 85 mW Shaper 110 mW
Timing 60 mV - Shared ADC/TDC
ADC
40 mW Total
295 mW/channel
Power Switching (preamp only..) If Preamp
Shaper ADC are running during collisions
only e.g. 1/100 duty cycle and 2 106
channels, then Total 295 10-6 x 2
106 x 1.3 10-2 7.67 Watts only !
A. Savoy-Navarro, SiLC Electronics, Victoria,
July 04
11
Preamp Linearity
Linearity better than 5
A. Savoy-Navarro, SiLC Electronics, Victoria,
July 04
12
Shaper response
5 MIP/step
Shaper response Gain 8mV/MIP over 45 MIP
A. Savoy-Navarro, SiLC Electronics, Victoria,
July 04
13
Noise
A. Savoy-Navarro, SiLC Electronics, Victoria,
July 04
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Preamp Power Switching
- Reset the feedback capacitor after switching
on and before switching off (Takes 5 us)
- Open and close two switches feeding Vdd Vss (
Ron100 W ) Power is zero when switched off
Signal
Vdd
Vss
Power off
Power on
Power off
Power on
Reset Feedback Capacitor
A. Savoy-Navarro, SiLC Electronics, Victoria,
July 04
15
ADC Comparator Time Walk simulations
Comparator linearity better than 0.5
A. Savoy-Navarro, SiLC Electronics, Victoria,
July 04
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Digital

• TDC counter
• ADC coding
• Memory
• Zero suppression and lossless data compression
• - Calibration management
• Virtual Silicon Library for UMC 0.18 mm
• - VHDL
• - Synthesizer interface
• - Mixed Design Layout tool

A. Savoy-Navarro, SiLC Electronics, Victoria,
July 04
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Silicon

• UMC 0.18 mm (Europractice)
• Standard 5 x 5 mm2 (to share)
• One full analog channel is 50 x750 mm2 only
• (SVX4 in TSMC 0.25 is 60 mm2 for 128 channels
• including analog pipe-lines, ADC, I/O)
• - Blocks of 2.2 mm2

A. Savoy-Navarro, SiLC Electronics, Victoria,
July 04
18
The readout of the Si-tracker pending (or not)
questions
1) Detector occupancy? Different according to the
detector location Outer central region
preliminary studies show occupancy ? 1
Inner central and forward regions preliminary
studies show occupancy of a

few , lt10 Work in
progress with Geant - based simulations size of
strips ?? 2) Double Multiple hit rates ?
Ambiguities to be estimated (tiling vs long
strips) 3) sparsification/pedestal substraction
on the detector F.E. ? Answer YES 4)
Pulseheight info (Q) needed? Answer YES to
perform cluster centroid and increase position
resolution down to 7 8 µs. (? 8 bit A/D ?)
? under construction a 10 bit A/D 5) Timing
information? Included in the FE design. The
principle possible
performances are being studied _at_
Paris test bench 6) DSP-like processing for
cluster algorithm and fast-track processing
algorithm
YES it will be done at what level in the
electronic chain ??? Under study while designing
FE 7) Power dissipation studies present results
? doesnt seem to be a major pb Indeed new
results both from FE mechanical cooling studies
indicate that passive (or light) cooling might be
an achievable goal.. 8) Power cycling included
in the design
A. Savoy-Navarro, SiLC Electronics, Victoria,
July 04
19
Output signals very preliminary exercise
Exercise performed with 3 external
layers of a Silicon tracker The idea is to
multiplex as much as possible the output signals
from the detector (already at the
digitization stage highly multiplexed A/D scheme)
A. Savoy-Navarro, SiLC Electronics, Victoria,
July 04
20
DAQ intermediate trigger very preliminary
ideas

• Based for instance on the current experience with
  the trigger system
• related to the tracking system in CDF, we are
  studying
• Fast-track trigger (or real time
  processing) system used for
• Doing fast clustering determining in real time
  the cluster centroid
• Doing fast tracking for stiff tracks (above 1 or
  1.5 GeV/c momentum) with the overall Si tracking
  information, and then linking to the µvertex.
• And similarly in the forward region, reconstruct
  a track segment.
• Other teams interested, as for ex
  HEPHY-Vienna.

A. Savoy-Navarro, SiLC-Electronics, Victoria,
July 04
21
Conclusions
Emerging new VLSI technologies - Silicon Deep
Sub Micron - Silicon-Germanium allow to
implement a highly integrated front end for SiLC
that does not degrade the detector resolution
within an affordable power budget. First
submission very soon. Already in the readout
design real time processing of silicon data
(sparsification, cluster centroid, fast tracking
algorithms ) must be included to profit from
interesting features of the Silicon
devices. Special attention is paid to packaging
and cabling issues to spare in material budget
FE readout Electronics including packaging
cabling are part of the Silicon detector.
A. Savoy-Navarro, SiLC Electronics, July 04