Liquid Argon Calorimeter Electronics Upgrading

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Liquid Argon Calorimeter Electronics Upgrading

• Andy Liu
• April 4, 2006

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Present FEB Structure

• Level 1 trigger on detector Resulting in analog
  pipeline (buffer)
• Data rate trigger rate 100k events/s, 128
  channels, 5 samples per event, 16 bits each
  sample, 1Gb/s (real data rate1.28Gb/s, 1.6Gb/s
  after 8B10B)

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FEB Upgrading Structure

• No level 1 trigger on detector no pipeline
  (buffer)
• Data rate 128 channels, 40M Samples /s, 16 bits
  each sample 82Gb/s (85 Gb/s if 64B66B, 102Gb/s
  if 8B10B)
• We MIGHT take part in the FEB design if manpower
  is permitted.

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FEB Upgrading Pre-Amp, Shaper, Gain Selector

• Pre-Amplifiers analog, low noise, NOT what we
  are good at
• Shapers (filters) analog
• Gain selectors can be analog or digital
• Pro and con if digital, double or triple ADCs
• All these three parts MIGHT be integrated into
  one ASIC

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A/D Converters

• A/D converters hard to design, AD41240 may be a
  good choice
• 12 bits
• 4 channels
• 40 MS/s
• 450mW / all channels active
• 0.25um CMOS
• Rad-hard tested up to 10Mrad
• Do evaluation first

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Data Flow Control - Functions

• Digital gain selectors (optional)
• Framing add control information to create a
  frame
• Data compression (zero suppression)
• Error detection and correction

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Data Flow Control - Framing

• Add ID information to create a frame BC, phase,
  ADC, event, cell,
• Current frame format is not band-width efficient
• In each 16-bit non-control word, bit 14 is always
  zero ? 6.25 band-width is wasted. If this bit
  had been deleted in the current FEB, the
  white-dot g-link chips would have been
  unnecessary.
• Each waveform has a uniform gain, but in current
  format each sample has two gain bits.
• Almost all control information (BC, Phase,
  event, cell) is sent 16 times.

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Data Flow Control - Data compression

• Initial test
• Test beam data, 200M Bytes, frame gap zeros have
  been deleted
• WinRAR 3.20, different compression mode,
  compression rate is 30 40
• A compression rate of 50 may save a lot.
• Requirements
• Lossless
• Real-time
• Evaluation in FPGA first the decompression part
  can be used in the future ROD .

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Data Flow Control - Error detection

• CRC is much better than parity in efficiency and
  performance
• CRC is an industrial standard algorithm and can
  be implemented very fast

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Data Flow Control - inputs and outputs

• Input pins 128 channels, 40MS/s, 16 bits for
  each channel ? 2048 bits, 40MHz
• Output pins 128 bits, 640 MHz (maximum LVDS
  rate)
• Too many I/O pins for one chip
• Must be a rad-hard ASIC (FPGA hard copy is not
  enough)
• Implemented in an FPGA first

Digital, not high speed, might be a good choice
for us to do
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Optical transmitters Working Direction

• If succeeded in one channel 2.5Gb/s LOC, continue
  to work on the optical transmitter for 12 ribbon
  fibers 40Gb/s
• If sLHC clock is still 25ns, and compression rate
  is better than 50, 40Gb/s is enough
• If succeeded in one channel 10Gb/s LOC, continue
  to work on the optical transmitter for 12 ribbon
  fibers 120Gb/s
• If sLHC clock is 10 ns, and compression rate is
  worse than 50, 120Gb/s is still not enough

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ROD Upgrading

• Level 1 trigger and digital pipeline
• NO DSP Use DSP module in FPGA instead
• No radiation hardness requirements
• We can take part in if the manpower is permitted

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Conclusion What can we do in the future several
years?

• Event builder design
• Link-On-Chip for ribbon fibers
• ADC evaluation
• FEB board structure study
• ROD board study
• Power Supply System ?