CMOS VLSI DESIGN

1
CMOS VLSI DESIGN

• Kasin Vichienchom
• kvkasin_at_kmitl.ac.th
• Lecture5

2
Logic Circuits
Combinational
Sequential
Output
(
)
Output
(
)
f
In
f
In, Previous In
Ex Logic gates, mux, decoder, adder
Ex Registers, counters, oscillators memory
Source Jan Rabaey
3
Sequential Logic
Model
Outputs
Inputs
COMBINATIONAL
LOGIC
Current State
Next state
Latche / Register
Q
D
CLK

• States can be stored by two storage mechanisms
• positive feedback (static register and latches)
• charge based (dynamic registers and latches

Source Jan Rabaey
4
Static Storage Elements
Vo1
Vi1
1
2
Vi2
Vo2
V
o
2
A
C
B

• Bi-stable circuit
• A and B are stable points
• C is a meta-stable point

Source Jan Rabaey
5
Static Storage Elements

With small noises it can move to either A or B
Stable at A and B
Source Jan Rabaey
6
Static Storage Elements
A
B
AB
A
AB
B
B
1
forced to be one
B
B
7
Static Storage Elements
A
B
AB
A
AB
B
0
forced to be zero
B
B
B
8
Static Storage Elements
RS Latches
S
Q
Q
S
Q
R
Q
R
S
Q
Q
S
Q
R
Q
R
9
Static Storage Elements
Modified RS-NAND with CLK
Basic SRAM cell
S
Q
Q
R
Source Jan Rabaey
10
Latches and Registers

• Latch level-sensitive
• stores data when clock is low (negative) or
  high (positive)

• Register edge-triggered
• stores data when clock rises (positive edge) or
  falls (negative edge)

D
Q
D
Q
Clk
Clk
pass
store
pass
store
pass
Clk
Clk
D
D
Q
Q
(stores when clock is low)
(stores when clock rises)
Source Jan Rabaey
11
Latches and Registers
Timing Definition and Characteristic
tsetup
thold
D
Clk
Q
td-t-q
Register (FF)
Latch

• Setup time and Hold time time interval needed
  for data to be stable before and after clock
  transition
• Clock-to-Q Delay delay time of a flip-flop
• Data-to-Q Delay delay time of a latch

12
Static Latches

• D Latch

D
Q
D
Q
Clk
Q
Clk

• Based on RS Latch
• Positive latch (active high)

Source Bahar
13
Static Latches

• Mux-Based Latches

• Feedback path creates a loop to hold data
• Change the stored value by cutting the feedback
  loop when clock is active

Source Bahar
14
Static Latches

• Mux-Based Latches implementation

CLK
CLK
D
Q
Q
CLK
CLK
D
CLK
Positive latch
Positive latch using nMOS pass transistor
CLK
CLK

• Need both CLK and CLK i.e. non-overlaping clocks

15
Static Registers (FF)

• Master-Slave Configuration

in
out
in
out
D
Q
clk
clk
Clk
in
out
D
Q
clk
Clk

• Combine two opposite latches resulting in a
  register

16
Static Register-DFF

• Mux-Based Master-Slave DFF

in
out
Q
D
clk
Clk
Source Bahar
17
Static Register-DFF

• Mux-Based Master-Slave DFF

Q
Q
M
D
CLK
Positive edge D-FF. Total number of MOS 22
Source Jan Rabaey
18
Static Register-DFF

• Mux-Based Master-Slave DFF

• NMOS pass transistor D-FF

CLK
CLK
D
Q
CLK
CLK

• Asynchronous set and reset D-FF

Source Weste and Harris
19
Dynamic Latches/Register
Static Latch
Dynamic Latch

• Feedback loop storage

• Charge-based storage

Source Jan Rabaey
20
Dynamic D-FF
Example
CLK
CLK
Q
D
CLK
CLK
CLK
Example
CLK
D
Q
CLK
CLK
CLK
CLK
D
Q
21
Dynamic D-FF
Pro reduce number of devices, clock load, high
speed Con more susceptible to noise, subject to
race conditions due to overlaping of CLK and CLK
CLK
CLK
Q
D
CLK
CLK
CLK
CLK
(1-1 overlap)
(0-0 overlap)
22
Race Free Dynamic DFF

• Clocked CMOS (C2MOS)

V
V
DD
DD
M
M
2
6
M
M
CLK
CLK
4
8
X
D
Q
C
C
L1
L2
M
M
CLK
CLK
3
7
M
M
1
5
Master Stage
Slave Stage
Source Jan Rabaey
23
Race Free Dynamic DFF

• Operation insensitive to clock-overlap

(a) (0-0) overlap
(b) (1-1) overlap
Source Jan Rabaey
24
Dynamic Latch

• True Single Phase Clock (TSPC)

• Need only one phase clock eliminate clock
  overlap problem
• Small number of transistor
• Two opposite latches give a DFF

Source Jan Rabaey
25
Modified TSPC

• Including logic in TSPC

• TSPC DFF

Source Jan Rabaey
26
Pulsed Triggered Latches

• Create an edge-triggered register from a latch by
  applying a narrow pulse to a latch

L1
L2
L
Data
Data
D
Q
D
Q
D
Q
Clk
Clk
Clk
Clk
Clk
Master-Slave Latches
Pulse-Triggered Latch
Source Jan Rabaey
27
Pulsed Latch

• Positive TSPC Latch gt Positive edge DFF

V
V
DD
DD
M3
M6
V
DD
CLK
Q
CLKG
D
CLKG
M
CLKG
M2
M5
P
X
M
N
M1
M4
(a) register
(b) glitch generation
CLK
CLKG
(c) glitch clock
Source Jan Rabaey
28
Pulsed Latch

• Hybrid (HLFF), AMD K-6 and K-7

P
CLK
P
1
4
Q
x
M
6
M
3
M
P
D
5
2
M
2
M
P
4
3
M
CLKD
1
Source Jan Rabaey
29
Latches and Registers

• Applications in digital systems
• memory element
• Store states in state-machine (digital
  controller)
• synchronization
• Pipelining

Synchronous timing Tmin tc-t-q tlogic
tsetup
30
Latches and Registers
a
a
REG
REG
log
Out
Out
log
CLK
CLK
REG
REG
REG
REG
b
CLK
CLK
CLK
b
CLK
REG
REG
T1
T2
CLK
CLK
Latency number of clock cycles it takes for the
data to propagate from the input to the output (
1gt3)
Throughput how often the output is updated (T1
gtT2)
Source Jan Rabaey