Lecture 21 Random Access Memory

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Lecture 21 Random Access Memory
CSCE 211 Digital Design

• Topics
• Sequential PLD Example
• GALs
• ROM revisited
• EEPROM, flash
• RAM
• Readings Chapter 9

November 18, 2008
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Overview

• Last Time
• GALs
• Sequential PLDs
• Twos complement on Sequential PLD
• New
• RAM
• Flash Ram
• http//en.wikipedia.org/wiki/Flash_memory
• Evaluations
• COEIT ? College of Engineering and Computing
• Honors College
• Next Time
• Labs bring kit to class
• Exam Thursday, December 11 - 200 p.m.
• Old Exam Handout
• Review (aka excuse for pizza)?

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ROM Varieties revisited

• ROM values in bits of words programmed at
  construction time
• PROM programmable ROM values in bits can be
  programmed by zapping components (e.g. diodes)
  after construction with a high voltage
• EPROM electrically programmable ROM
• EEPROM Electrically erasable programmable ROM
• Flash memories EEPROM in which erasing is done
  in large blocks (blocks are erased in a flash)

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Fig 9-10 EPROM with floating-gate

• EPROM with floating gate MOS transistor
• Floating-gate
• Not connected
• Surrounded by high-impedance material
• Program it
• Put high-voltage on non-floating gate
• Negative charge leaks to floating gate
• Turns off the transistor
• Guaranteed to retain 70 of charge for ten years
  (non-volatile!)

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EPROM packages
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Static RAM Cell

• RAM Random Access Memory
• Sequential access devices??
• ROMS are random access also
• Static RAM Cell
• D flip-flop with control logic fig 9-20

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8x4 static RAM

• Notes
• SRAM static RAM
• 3 addr lines ? ___ words
• __ bits per word
• WE_L
• CS_L
• OE_L
• DIN3 -

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Static RAM timing - READ
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Static RAM timing - WRITE
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Bidirectional Bus

• Bidirectional bus read and write on same lines

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Synchronous Static RAM - SSRAM

• Clocked interface for control, address, and data
• Synchronized with clock signal on bus
• Latches save addr, control, data lines on rising
  edge
• AREG, CREG, INREG
• Operation performed during subsequent cycle

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Timing of SSRAM - Fig 9-29
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Dynamic RAM

• Static RAM Cell
• D flip-flop control 6 transitors
• Dynamic RAM
• 1 transitor
• 1 capacitor
• Operation
• Reading
• Writing
• Capacitor leaks ? refreshing required

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Synchronous DRAM Structure
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Refreshing

• Charge stored in the capacitor leaks out
• Needs to be refreshed
• Refresh Cycle 64 milliseconds
• Refresh an entire row at a time
• E.g. newer RAMs have
• 4096 rows
• Refreshed once every 64 ms
• 64ms/4096 one row every 15.6 µs

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Varieties of RAMS

• Static fastest most expensive used for caches
• Whats a cache? Take 212
• Dynamic RAM
• SDRAM synchronous DRAM (clock from bus/CPU)
• SSDRAM
• DDR SDRAMs - Double data rate transfers data
  on both edges of the clock

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Flash Memory

• http//en.wikipedia.org/wiki/Flash_memory

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