HCal SiPM ASIC Status

1
H-Cal SiPM ASIC Status

• LAL Orsay
• S. Blin, J. Fleury, C. de la Taille, G. Martin,
  L. Raux

2
Contents

• SiPM Readout Chip
• Reminder chip Architecture
• Prototype Measurement
• DAC performance
• Preampshaper CRRC2 Performance
• in Calibration Mode
• In Physics Mode
• Production Chip
• Chip Modifications
• Production schedule
• Production cost
• Prospective

3
Channel architecture for SiPM

• 18-channel chip CMOS 0.8 µm
• Compatible with ECAL read-out

Submitted in June 2004 Received in
September 2004
4
Linearity DAC

• Linearity 18 channels
• 8 bit-DAC
• Excursion 0-5V

• Residuals DAC (V) CH0 in volts
• Non linearity due to a mismatch in the current
  mirror

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Noise vs DAC

• SPE mode Cf0.1 pF tau12ns 1 SPE 15 mV
• DAC noise Rf2(n2qI4kT/Rf) with Rf50k and
  I50µA 300 nV/sqrt(Hz) (compared to 1.6 nV
  preamp)
• Good agreement with (complete) simulations, but
  unsufficient filtering due to low DAC output
  impedance and too large series resistance to the
  filtering 100 nF
• A factor 1000 (60dB) attenuation needed gt low
  pass filter at 1kHz 10 kohm100nF

The DAC has been redesigned to reduce the
bandwidth and consequently its noise contribution
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Chip modifications on DAC

• Buffer on DAC and Read Register output

0.2pF
CMOS switch
50kO
Resistance added to filter DAC Noise
I_mirror
Preamp input
10kO
OTA
Rprot50O
5pF
50O
Capacitance added to have a better OTA stability
Vref
Unnecessarry resistance
100nF
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MIP response

• 1 MIP 16 p.e. injected electronically (no
  detector)
• Physics mode (left plot) Vout 30 40 mV tp
  150 180 ns
• Calibration mode (right plot) tau 24 ns Vout
  75 mV tp 45 ns

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Measurements results MIP mode 200 ns

• MIP electronic injection 5 mV in 270pF ( 16
  p.e. G 1E6)
• Dynamic range 80 MIPs (_at_ Cf0.4pF)
• Good agreement with simulations, but significant
  noise increase with DAC setting

• The injection capacitance has been increased
  from 5pF to 10pF
• simulation done with the electronics injection
  (5mV in 270pF)

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Linearity measurement (physics mode)

• Cf0.4pF ,Tau200ns
• Voltage swing 2.1V
• Dynamic Range 1-80 MIP
• Linearitylt1

80 MIP
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Measurements results SPE mode

• Single photoelectron response 1 SPE 0.16 pC
• SPE electronic injection 0.3 mV in 270pF

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SiPM Connection

• 1 SiPM connected with new biasing scheme
• HV 45 V

HV
8-bit DAC
100nF
100kO
Need 10k here
SiPM
input
50O
ASIC
100nF
12
SPE spectrum

• Cf0.2pF, Tau12ns

pedestal
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Schedule

• Prototype Submission in June 2004
• Prototype Delivery in September 2004
• Test and validation with SiPM in October 2004
• Production (1000 chips) of the validated version
  with modifications on the DAC in November 2004
• Systematic test board Development in December
  2004
• Production Delivery expected in January 2005
• Systematic chips test in February 2005
• Chips available for the collaboration by
  March-April 2005

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Production cost

• Silicon 1000 dies (area 10mm² )? 2 wafers
  needed 21.4 k Euros
• Expected Production yield 80
• Package PQFP-100 4.1 k Euros
• Total 25.5 k Euros

15
Prospective and Conclusion

• Chips available for the collaboration
• Possible Development in 2005 chip of a Prototype
  in CMOS 0.35um
• Prototype dedicated for SiPM
• Based on OPERAROC Chip Architecture current
  conveyor
• less noisy in Calibration Mode
• Development of ADC to be embedded in the
  front-end chip

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Measurements results MIP mode 150 ns

• Low noise mode Rc short circuited
• Dynamic range 80 MIPs (_at_ Cf0.4pF)

The injection capacitance has been increased
from 5pF to 10pF
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Measurements results SPE mode

• Single photoelectron response 1 SPE 0.16 pC
• SPE electronic injection 0.3 mV in 270pF