ASSET: Automated Synthesis of Embedded Systems

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ASSET Automated Synthesis of Embedded Systems

• M. Balakrishnan
• Embedded Systems Group, IIT Delhi
• January 22, 2002

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Outline

• Introduction
• Hardware estimation
• Software estimation Integration
• Hardware - Software partitioning
• C2VHDL and Co-synthesis
• Development of communication models and Interface
  Synthesis
• FU modeling for VLIW ASIPs in Trimaran
• Other Projects

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Asset Framework Flow
Application Specification
Application Analysis Profiling
Comm. Estimations
Storehouse SUIF
SW Estimations
HW/SW Partitioning
HW Estimations
SW Synthesis
Interface Synthesis
HW Synthesis
Co-simulation and Verification
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Target Architecture
Memory
Processor
Arbiter
ASIC1
ASIC4
ASIC3
ASIC2
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Target Architecture
Processor
ASIC1
Memory
FU model
Co-proc model
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Software Estimation Integration

• Students
• Nikhil Bansal and Hemant Gupta
• Status
• - SW estimator working with operation counts
• - Integration framework ready
• This semesters work
• - Proper parameter extraction suggested by Manoj
  and Joshi
• - Considerations of machine independent
  optimizations
• - Integration of communication estimation and
  Joshis work
• - Co-simulation using modelsim and verification

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Hardware Estimation

• Student
• Arun Kejariwal
• Status
• - HW estimator redesign done with area, clock
  and bounds on execution times
• This semesters work
• - Register and memory estimation
• - Interconnects estimation
• - Fine tune the library
• - Explore array packing for the memory

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C2VHDL and Co-synthesis

• Students
• Amit Chabra and Amarjeet Singh
• Status
• - VHDL getting generated for FU and co-proc
  models
• This semesters work
• - Define the architecture template
• - Synthesize and implement the architecture
  template on ADM-XRC board with and
• without Leon
• - Extend/fine tune the C2VHDL as per requirement
  
• - Provide feedback to HW estimator

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Development of Communication Models and Interface
Synthesis

• Student
• Shonali Gupta
• Status
• - Communication models developed for PCI
• This semesters work
• - Validate the communication models using
  estimators
• - Experiment with various communication modes
• - Build a library of interface components

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FU Modeling for VLIW ASIPs in Trimaran

• Students
• Bhuvan Middha and Varun Raj
• Status
• - Incorporated capability to add a new FU in
  Trimaran
• - Automated the framework as well as inserted
  mode for bypassing the modifications
• This semesters work
• - Modify HMDES to reflect the number of register
  file ports as resources
• - Modify scheduler to constrain the usage of
  these ports at different cycle times
• - Introduce support for MIMOs with load/store
• - Perform case studies

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Collision Detection Case Study

• Students
• Nakul Garg and Anuj Bindal
• Status
• - Case study done for one type of
  partitionitiong
• This semesters work
• - Get better partitions using asset tools
• - Experiment with different application
  partitions
• - Provide feedback to used asset tools

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SUIF2 Evaluation

• Student
• Amit Jain
• Goals
• - Study SUIF2
• - Port different asset tools to SUIF2 and verify
  operations

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Library Development

• Student
• Amit Agarwal
• Goals
• - Develop the library required by HW estimator
  for FPGA and ASIC
• - LEON synthesis and implementation on ADM-XRC