Buses

1
Buses

• AMS-505
• Serial 2.7

2
Review
3
Buses

• System Bus
• Control, Address, Data
• Signaling, timing, contention
• Master / Slave
• Bus Types
• ISA, PCI, VME, etc

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Triple Bus Architecture
5
Triple Bus Architecture

• Triple bus architecture has distinct multiple
  connections for handling each of data, addresses,
  and control signals.
• Since busses connect to many different subunits,
  and it only makes sense that a bus can only carry
  one item of information at a time, there must be
  a strict set of controls to coordinate bus usage.
• These controls, or protocols, govern how the
  various parts of the computer use the bus to send
  and receive information.

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Triple Bus
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Buses

• Data Buffer - Latch data
• Address Decoder - Are you talking to me?
• Control Logic - Diverse uses
• Bus Master - Whose in charge of this data
  transfer? (Usually the CPU)
• Slave - Bus Master uses address lines to select
  other participant in transfer.
• Bus Master also uses control bus lines to signal
  the direction of transfer and how much data.

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Master / Slave
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Buses

• Throughout the transfer process, various control
  lines are used to signal when the address has
  been placed on the bus, sort out which of several
  possible slave units are indicated, tell when
  data has been placed on the bus, inform when the
  data has been drawn off the bus by the
  destination unit, etc.
• For a DMA transfer, the CPU gives control to
  another unit to act as the bus master.

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Timing

• Timing constraints arise from the fact that logic
  gates require some fixed period of time to
  undergo each change.
• Some amount of time is required for a voltage to
  travel the length of a given bus.
• A Timing Diagram is a pictorial representation of
  the sequence of events which must occur during
  the transfer of data between units, as between an
  I/O interface and the CPU.

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Timing Diagram
12
Contention

• What if two or more devices want to become the
  Bus Master at the same time?
• Answer Bus Arbitration
• Eg A bus with 5 devices, each of which can act
  as the Master...

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Arbitration
Bus Request
Busy
5v
in
in
in
in
in
out
out
out
out
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Bus Types

• ISA (EISA)
• Industry Standard Architecture (1984)
• 16 bit data bus (32 for EISA), 24 bit address bus
• 8 Mhz
• VESA (Local bus)
• Video Electronics Standard Association
• 32 data lines
• 40 MHz

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Bus Types

• PCI (Local Bus)
• Peripheral Component Interface (1992)
• 32-bit address and data bus
• 33 MHz
• address lines can be multiplexed to 64 bits and
  bus can clock at 66 MHz (Pentium)

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PCI / ISA Diagram
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Bus Types

• VMEbus (VME64)
• VERSAmodule Eurocard
• full 32 bit data and addressing (64 bit data and
  address buses for VME64)
• Asynchronous
• Up to 500 Mbyte/sec transfer rates

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Today...

• PC100 (Intel)
• 64 bit buses
• 83 MHz
• FSB
• Front Side Bus (Intel)
• 64 bits
• 150 Mhz

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Next

• System Organization