JET Algorithm

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JET Algorithm

• Attila Hidvégi

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Overview

• FIO scan in crate environment
• JET Algorithm
• Hardware tests (on JEM 0.2)
• Results and problems
• Ongoing work on jet code
• Other work in Stockholm
• Summary

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FIO scan in crate environment (one of two JEMs)
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Delay scan for individual FPGAs
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Delay scan for two JEMs (same deskew clock
settings)
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It is important to equalize timing between JEMs
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Hardware tests of Jet algorithm

• Originally only jet multiplicities recorded
  insufficient for diagnostics. New firmware was
  needed.
• All inputs and outputs needed to be recorded.
• Same spy memory and software as for FIO scan.

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JET Algorithm Results

• All input data is received properly (?).
• Synthesis tool reports maximum delay of 11.2 ns
  and 26.4 ns, for 80 and 40 MHz clocks,
  respectively.
• This is the maximum achievable result for current
  VHDL code.
• Results from hardware tests show random errors!

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Most likely cause of the problem

• Only adders still use 5-bit serial arithmetics
• Virtex architecture more suited to parallel
  arithmetic with fast-carry chains.
• Adders are the slowest component of the
  algorithm.
• The errors are intermittent, suggesting timing
  problems
• Sums occasionally wrong.
• Sometimes cause incorrect threshold passes
• More often give wrong ROI positions for random
  data
• The timing problem of the adders can not be
  resolved without a major rewriting.
• JET algorithm is being rewritten from scratch.

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New design for the Jet code

• It will be flexible. Generic variables will
  decide the configuration.
• Try to minimize size and latency.
• The code has to be short, so that one can modify
  it easily.
• Use only parallel arithmetics, and take full
  advantage of the fast carry architecture
  available in Virtex FPGAs.
• Let the synthesis tool do the hard work.
• All the parts have to be tested VERY carefully so
  we really get what we expect.
• It needs to work

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Making it flexible means
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What could be done better ?

• Putting all summations and the local maximum
  finder in the first clock cycle allows us to
  remove the pipelines.

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What could be done better ?

• It is important to remember that multiplexers
  (21), adders and comparators have equal sizes,
  since they use the same logic resources.

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What could be done better ?
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Generating the adder trees for the Jet algorithm
(new version)
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Generating the adder trees for the Jet algorithm
(new version)
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Other work in Stockholm

• Work on the CMM code for Jet merging (Sam
  Silverstein).
• Based on the CP merger design simple
  modifications to accomodate 16 JEMs
• Simple version no special FCAL treatment
• Have completed crate merger FPGA source for both
  crate and system mergers
• Next steps
• Compile and simulate crate merger designs
• System merging FPGA (not much to do)

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Summary

• FIO scan look promising.
• Jet code didnt work, is being rewritten from
  scratch.
• The new Jet code seems promising.
• Work on the CMM goes well.