High Quality Robust Tests for Path Delay Faults

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High Quality Robust Tests for Path Delay Faults
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Outline

• Introduction
• Exciting worst case delay
• Side-input transitions
• Pre-initialization
• Test generation
• Experimental results
• Conclusions
• Further Discussion
• Time dependent model
• Impact of timing on delay
• Timing oriented ATPG

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Introduction

• Motivation Classical robust tests do not always
  invoke worst case path delays
• Objective Generate high quality robust delay
  tests
• Approach
• Develop new test conditions for high quality
  robust tests for a path that take into account
  switch-level delay phenomena
• Construct an ATPG to generate robust tests that
  invoke the maximal delay along a path

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Exciting Worst Case Delay Two Pattern Tests

• Classical definition of robust test does not
  guarantee excitation of worst case delay
• Side-input (SI) target gate On-path gate with
  to-non-controlling transition at on-path input
• Desired SI condition (for exciting worse case
  delay) to-non-controlling transitions at the
  side-inputs of every SI target gate

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Exciting Worst Case Delay Desired Side-Input
Conditions

• For SI target gates, off-path inputs must have
  to-non-controlling transitions
• For other on-path gates, the classical conditions
  of robustness should be used
• Desired side-input transitions for on-path
  NAND gates

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Exciting Worst Case Delay Impact of Internal
Capacitances on Gate Delay

• For 3-input NAND with a 1?0 transition at its
  output

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Exciting Worst Case Delay Pre-initialization

• Activating a rising transition at X by V1?V2
• C Status of C after application of V1 but
  before
• application of V2
• The ratio increases as the number of inputs
  increase
• Pre-initialization vector V0 is required to
  pre-charge the internal capacitance C to excite
  the worst case delay

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Exciting Worst Case Delay Pre-initialization
(Contd)

• Procedures
• Check if pre-initialization helps excite longer
  delay
• If yes, find the best pre-initialization vector
  (V0)

V1
C1 discharged C2 charged C3 charged
C1 discharged C2 ? C3 ?
Detail
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Exciting Worst Case Delay Enhanced Gate Level
Model

• Capture required switch-level data in gate level
  description

?
Z is closest to gate output
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Test Generation Procedure

• Two vectors Generate a two-pattern test ltV1, V2gt
  that (a) satisfy the classical conditions for
  robustness and (b) maximize the number of gates
  at which desired conditions are satisfied
• Third vector For the given two-pattern test ltV1,
  V2gt, find a V0 such that ltV0, V1gt help excite
  worst case delay by pre-charge/discharge
• Backtrack If no such V0 exists, backtrack to
  generate a new two-pattern test ltV1,V2gt,
  followed by a search for V0

Detail
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Experimental Results

• More than 50 of robustly testable paths have
  tests of different qualities
• 19-30 of robustly testable paths have tests of
  ideal quality
• For 80 of ltV1, V2gt generated, a V0 can be found
  so that ltV0, V1, V2gt is a high quality test

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Experimental Results (Contd)

• Quality distribution for all tests for selected
  paths in S208
• The probability of a classical robust test being
  a high quality test is small

 
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Conclusions

• High quality robust tests are proposed to excite
  the worst case path delays
• A new test generator developed
• New conditions for robustness and
  pre-initialization
• Conditions defined in a timing independent manner
• Transistor level delay phenomena captured at gate
  level
• Optimization oriented ATPG
• Results of experiments
• The probability of a classical robust test being
  a high quality test is small
• 20-30 of robustly testable paths have 2-pattern
  tests of ideal quality

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Time Independent Model Advantages

• The tests will not be invalidated by timing
  variation
• Different timing assumptions can be used to
  generate time dependent tests for different
  faults, e.g. ground bounce, and crosstalk, while
  using the above conditions to guarantee
  robustness
• The same test generation approach can be applied
  to a time dependent model by changing the
  objectives and cost functions for TG
• We simplify the problem by separating time
  dependent and independent considerations

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Time Independent Model Problems

• In practice, not all high quality robust
  conditions (HQRCs) help excite the worst case
  delay with timing.
• In practice, not all helpful HQRCs increase the
  same amount of target path delay with timing.
• on-path transition
  propagation
• high quality robust
  conditions (HQRC)
• Solution Timing information

Back to test generation
Back to experimental results
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Impact of Timing on Gate Delay

• Side input transitions affect the target path
  delay only when input skew ? is small
• Timing is critical to effects of delay phenomena
• ATPG needs to have the capability to handle
  timing information

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Timing Oriented ATPG Motivation

• High quality tests exist
• Number of high quality tests is significant
• A timing oriented ATPG is required to identify
  one of those

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Timing Oriented ATPG Motivations (Contd)

• Worst case delay excitation
• Robust testable paths
• Have many high quality tests
• Timing is necessary to capture the true delay
  phenomena
• Non-robust testable paths
• Timing is necessary to develop tests
• Timing is necessary to capture the true delay
  phenomena
• Crosstalk
• Need timing to capture the effect of crosstalk
• Consider process variation in test generation
• Need timing to capture process variation

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Timing Oriented ATPG Implementation

• Four components delay model, timing simulation,
  processing of test conditions, search engine
• Delay model
• Capture target delay phenomena
• Provide information for decision making in ATPG
• Consider timing ranges and partially specified
  input values
• Timing simulation
• Simulate the circuit according to the chosen
  delay model
• Need to deal with unspecified values
• Need to handle hazards

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Timing Oriented ATPG Implementation (Contd)

• Processing of test conditions
• Test conditions logic and timing
• Operations forward/backward propagation and
  implication
• Enhance the processing of logic conditions
• Develop the processing of timing conditions
• Search engine
• Search for the optimal test that excites the
  worst case delay

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Following pages are hyper linked pages for High
Quality Robust Tests
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Exciting Worst Case Delay Pre-initialization
(Contd)

• An on-path gate is a pre-initialization (PI)
  target gate iff
• the on-path input has a to-non-controlling
  transition
• at least one side-input has the same transition
  as the on-path input
• PI target gates are subset of SI target gates
• Pre-initialization is required if there exists
  one or more PI target gates

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Exciting Worst Case Delay Pre-initialization
(Contd)

• Pre-initial bound (for a target gate) farthest
  gate input from the output where a controlling
  value is implied by V1 of a two pattern test ltV1,
  V2gt
• The pre-initial bound is a function of input
  connections

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Exciting Worst Case Delay Pre-initialization
(Contd)

• Pre-initialization rules to ensure high quality
  test
• Static controlling value should be implied at the
  pre-initial bound by ltV0, V1gt
• V0 must imply the gate non-controlling value at
  all inputs driving series transistors between the
  gate output and the pre-initial bound

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Test Generation Objective and Approach

• Objective Excite worst case delay
• Approach Optimization oriented
• Assign transitions to all on-path lines
• Specify
• conditions required for robustness
• desired SI values for high quality tests
• Construct decision tree for PODEM and search for
  solutions

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Test Generation Test Quality Metrics

• Quality of a path number of SI target gates for
  which desired SI conditions are satisfied
• IQ(P), Ideal test quality of a path P number of
  SI target gates in P
• UQ(P,a), upper bound of test quality of a path P
  number of SI target gates that may satisfy SI
  conditions along the given path for a given input
  assignment a
• TQ(P,t), test quality of a path P for a given
  test t
• Highest quality (HQ(P)) of a path MaxTQ(P, t)
• Lowest quality (LQ(P)) of a path similarly
  defined

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Test Generation PODEM Based Decision Tree

• Node a primary input selected as the objective
  of PODEM
• Branches of a node associated with values
  assigned to this node
• After each branching step,
• calculate
• UQ(P,a)
• TQ(P,t) if a test is found
• check and do
• If test t is found and TQ(P,t) gtHQ(P)
• best test t, HQ(P) TQ(P, t)
• If UQ(P,a) ? HQ(P) backtrack
• If TQ(P,t) IQ(P) stop

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Test Generation Traversing PODEM Based Decision
Tree

• Procedure for finding an primary input as the
  objective for value assignment
• 1. Use backward implication to find the necessary
  assignment at primary inputs
• 2. If not all necessary assignments are
  satisfied, assign a value to an input for
  justifying a necessary assignment
• 3. Repeat 2 until all necessary assignments are
  satisfied (a test found)
• 4. Assign a value to an input for justifying a
  desired SI transition if possible
• 5. Repeat 4 until no more SI transition can be
  justified
• Whenever a contradiction is found, backtrack

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Test Generation Example

• Target path 1 12 15 9 11 10
• Necessary input assignment
• L1 , L7 , L5
• IQ 3
• HQ -1

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Time Independent Model Problems

• To resolve this problem we require timing
  information.
• Problem The increase in delay of target path
  delay depends on the input skew (?).
• on-path transition
  propagation
• high quality robust
  conditions (HQRC)
• Solution Timing information