Process Description and Control

1
Process Description and Control

• Chapter 3

2
Review Question (chapter 2)

• Why should the OS cause the processor to
  interleave execution of more than one process at
  a time?

3
Multiprogramming or Multitasking
Allows the processor to execute another program
while one program must wait for an I/O device.
Run A
Run A
Run B
Run B
Wait
Wait
Time
4
Figure 3.4

• Put (b) on top of (a)

Dispatch
(a)
Enter
Exit
Pause
Processor
Exit
Enter
Dispatch
(b)
5
Refining the Original 2-State Model

• Refinement of Not Running State
• Newly Created Process
• User has made request to create process, but no
  resources, other than PCB
• have been allocated to it yet.
• Terminated Process
• Program complete, but OS has not yet reclaimed
  resources.
• Blocked
• A process that has all resources it needs to
  execute, except the CPU.
• Ready
• A process that only requires the CPU in order to
  run (it has been granted all other resources that
  it requested).

6
The 5-State Model

New No resources (except PCB) have yet been
allocated Blocked Needs some resource other
than the CPU Ready Only needs the CPU in
order to run Running Has all resources,
including the CPU, that it needs to
run Terminated Completed, but still has some
resources that need to be reclaimed by OS Note
There may be many different Ready and Blocked
Queues, corresponding to different priorities
and events.
7
Long Term Scheduler

The Long Term Scheduler is responsible for
granting the basic resources, e.g., process
control blocks, to new processes and for
re-claiming resources from terminated
processes.
8
Short Term Scheduler

The short term scheduler determines which of the
Ready processes should be scheduled next.
9
Data Structures Maintained by OS

• Status of Resources
• Main memory
• What is currently available
• Secondary memory
• What is currently available
• Mirrored on disk
• Status of devices, e.g., printers
• Status of Processes
• Well now look more closely at the PCB contents

10
Typical PCB elements

• Process Identification
• Identifies process, parent process, group,
  associated user, privileges
• Processor State Information
• Register Content
• User Visible registers
• Control and status registers
• Process Control Information
• Process State
• Could be implicit (i.e., on a wait queue for a
  particular event)
• Priority
• Scheduling-related information
• Data Structuring Information (links to other
  PCBs)
• Pointers to Memory Management Structures
• Miscellaneous Resources Owned/Used (e.g., files
  that are open)

11
System Calls,Traps,and Interrupts-- or
--Everything you always wanted to know about
Context Switching
12
Context Switching

• context switch - switching between the execution
  of a user process and the operating system (or
  vice versa)
• what happens?

13
What happens during a Context Switch?

• Assume first that process B is running

14
What happens during a Context Switch?

• Then assume that there is either a trap,
  interrupt or service call
• Any of these causes the operating system to
  begin to execute

PC
IR
...
R0
...
Rn
OS Data
OS code
PCBA
PCBB
PCBM
...
ProcessA
ProcessB
ProcessM
...
main memory
15
What happens during a Context Switch?

• The Operating System then copies Processs Bs
  register information into Processs Bs Process
  Control Block and puts its own values into the
  registers.

PC
IR
...
R0
(2)
...
Rn
(1)
OS Data
OS code
PCBA
PCBB
PCBM
...
ProcessA
ProcessB
ProcessM
...
main memory
16
Context Switch Causes

• When a program terminates
• When a program makes a service call
• When a program traps (tries to execute an illegal
  instruction)
• When a device interrupts (needs servicing)
• Examples
• printer needs more data
• DMA device ready to transfer more data
• mouse click
• hardware clock interrupts

17
Interrupts

• when interrupts are enabled, the cpu checks
  
• whether there is an interrupt on the system
  bus
• after it executes each instruction.
• there is often a disable interrupts
  instruction
• (after execution, the cpu does not check the
  bus -
• until it executes a re-enable interrupts
  instruction)
• sometimes interrupts can be selectively
  disabled
• (cpu only checks for certain interrupts
  signals on
• the bus)

• When an interrupt occurs
• the cpu loads the instruction register with
  the address of the
• appropriate interrupt handler for that
  interrupt
• the address is found in the hardware vector
  table
• the address refers to a location in the
  operating system code

18
Traps

• Traps occur when a program executes an illegal
  instruction.
• process status word (PSW) register is checked
• arithmetic error
• divide by 0, integer-overflow, etc.
• control is transferred, via vector table, to
  trap handler in the OS code, which usually
  terminates program abnormally
• copy of memory and registers dumped to file
  (core)

• illegal address referenced
• e.g., segmentation violation
• handled similarly to arithmetic error

• attempt to execute a privileged instruction in
  non-priv. mode
• priv. bit in PSW set when executing OS kernel
  only
• some processors have more than 2 modes
• e.g., pentiums have 4

19
Service Calls

• Similar to subroutine call, except
• made from user process to OS code
• separate stack sometimes used
• x86s (including pentiums) use this
• use concept of gates

user
(1)
OS kernel
(2)