GPS Waypoint Navigation - PowerPoint PPT Presentation

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GPS Waypoint Navigation

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Shanshan Ma (M2-4) Design Manager: Zack Menegakis. Presentation 12: Short ... Full chip layout w/ overlaid floorplan ~ 8 Slides. By: Nan. 9. Issues & Solutions ... – PowerPoint PPT presentation

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Title: GPS Waypoint Navigation


1
GPS Waypoint Navigation
  • Team M-2
  • Charles Norman (M2-1)
  • Julio Segundo (M2-2)
  • Nan Li (M2-3)
  • Shanshan Ma (M2-4)
  • Design Manager Zack Menegakis

Presentation 12 Short Final Presentation April
26, 2006
Overall Project Objective Design a low-power
chip that navigates an aircraft to pre-determined
waypoints.
2
Status
  • Design Proposal
  • Architecture Proposal
  • Size Estimates / Floorplan
  • Gate-Level Design
  • Spice Simulations (Schematic Layout)
  • Power
  • Delays
  • Functional Block Verification
  • Timing Verification
  • Layout (DRC LVS)
  • Functional Blocks
  • Global (99)

By Charles
3
Marketing
  • What is a GPS Waypoint Navigator?
  • Uses Applications
  • Hardware VS Software
  • Very low-power
  • Compact

2 Slides
By Charles
4
Design Process
  • Description
  • Requirements
  • Math
  • High-Level Simulations
  • Behavioral Verilog
  • Structural Verilog
  • Schematics
  • Layout

5 Slides
By Nan
5
Algorithm Description
  • Brief overview
  • How it works?
  • Clock Breakdown
  • Why so many???
  • System Flow
  • System Inputs ? Blackbox Outputs ? Blackbox
    Inputs ? SystemOutputs

15 Slides
By Shanshan / Julio
6
Verification
  • MATLAB
  • Behavior Verilog
  • Structural Verilog
  • Schematics
  • Begin timing verification serialization
  • Layout
  • Timing (post layout)

10 Slides
By Julio
7
Floorplan Evolution
  • Original Floorplans
  • Description
  • Why were they modified/scrapped?
  • Latest Floorplan
  • Description
  • Why is it acceptable?

5 Slides
By Shanshan
8
Layout
  • Layer Masks
  • Full chip layout
  • Full chip layout w/ overlaid floorplan

8 Slides
By Nan
9
Issues Solutions
  • Grouping Re-grouping
  • Initial I/O count gt 200 ? Serialization
  • Architecture Complexity
  • Trade off between I/O pins accuracy
  • 1 ft. Accuracy ? 4 Clocks
  • Chip Interface (i.e. unit conversions)
  • Blackbox or no Blackbox???
  • Overall Design Size
  • Transistor Count
  • Bus Sizes / Buffers
  • ECE File Space
  • Power
  • Simulations
  • Cadence

3 Slides
By Charles
10
Specifcations
  • Pin Specs
  • Circuit Specs
  • Transistor Counts
  • Area
  • Density
  • Delays
  • Why they dont mean anything???
  • Power

3 Slides
By Charles
11
Conclusion
1 Slide
By Charles
12
Updates
  • Layout 99 done as of 85959am this morning
  • Finished analog sims for all functional blocks
  • Cadence limits our top-level testing capabilities

13
(No Transcript)
14
Questions
Total Slides 54 Slides
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