Operating Systems for Reconfigurable Computers

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Operating Systems for Reconfigurable Computers
The development of the first operating system for
a Reconfigurable Computer
Grant Wigley
Advanced Computing Research Centre University of
South Australia
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Overview

• What is a Reconfigurable Computer (RC)?
• Why multitask a RC and why use an operating
  system (OS)?
• What are the major design stages in creating FPGA
  designs and why incorporate them into the OS?
• The OSs specific algorithms
• Future Work

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A Reconfigurable Computer

• Include reconfigurable logic, currently
  Field-Programmable Gate Array (FPGA) technology,
  as part of the processing resource
• Speed up computations by implementing algorithms
  as circuits, thereby eliminating fetch and decode
  cycles and exploiting concurrency

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Example SPACE.2 System

• PCI Bus based co-processing board
• Alpha UNIX host
• Controlled via device driver
• Array of XC6200 FPGAs

Inter-board network on secondary backplane
Computing surface 8 x XC6200 FPGAs
Clock module
Buffer RAM module
Control logic module
SPACE.2 board
64 bit PCI local bus on host motherboard
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Reconfigurable Computing

• For RC to become mainstream then it must have
  appropriate OS support
• As the number of gates rapidly increases the
  efficiency of area becomes less important than it
  was
• The wasted area due to the OS can be traded for
  an increase in ease of use of the RC

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Multitasking an FPGA??

• With the development of the partially
  reconfigurable FPGA, designers are looking
  towards multitasking Reconfigurable Computers
• Multitasking a RC will have the ability to
  concurrently execute more than one dependent or
  independent task thus increasing the RC
  throughput and reducing the average waiting time

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Why an OS for RC?

• Multitasking an FPGA will require an OS to manage
  the loading, swapping and allocation of the tasks
  to the FPGA surface
• As the status of the FPGA changes in time, the
  designs will have to be completed at run-time,
  and not statically compiled
• This requires the partitioning, placement and
  routing to be handled by the OS

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Problems with Run-time Design

• The partitioning, placement and routing
  algorithms are NP-hard and require long execution
  times and if the system is to be online these
  choices have to be made as quick as possible
• Difficult for an automatic process to make design
  decisions for logic circuits and get it right all
  of the time

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The Design Stages

• Allocation
• Deciding which part of the FPGA is available and
  can accommodate the incoming task

FPGA
FPGA
Incoming task
Available Space
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Dynamic Partitioning

• Deciding how to fit a task graph to the available
  hardware

Circuit Design
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Placement

• What nodes of the design get mapped to what FPGA
  cells?

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2
4
1
5
3
6
5
1
4
6
2
Allocated, Partitioned Circuit
FPGA partition
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Routing

• Determining a path between two points to create
  an electrical connection

B
A
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The Implementation Details

• Based on the Client/Server model
• Assumes 2-input lookup table
• X lines of C code
• Compiled under gcc, using Linux 6.2 OS running on
  a 433 Mhz Celeron Laptop

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General Specifics

• Uses sockets and ports for connectivity
• Can accept any number of clients
• 3 - digit protocol for communication
• Host password file for security

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Uploading a User Circuit

• File Format
• User sends the file to the server and the server
  caches it until the user leaves

5 1 1 2 3 2 1 3 5 3 1 1 0 4 1 3 5 5 1 0 0
Total no. of nodes
Node connection Number
Node Number
Size of node
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Allocation Algorithm

• Stores the file into a linked list structure
• Calculates the total area required for the design
  and determines the optimal circuit dimensions
  (the OS limits it to rectangles)
• Determines if there is available FPGA logic
• If the circuit is unable to be placed in its
  current shape it calculates the largest FPGA
  logic area available

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Dynamic Partitioning Algorithm

• The algorithm is based on the Temporal
  Partitioning Algorithm by Gajjala Purna
• Calculates the As Soon As Possible (ASAP)
  execution levels of each node
• Allocates the nodes in order of ASAP level to the
  partition until the partition is full

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The Partitioning Algorithm

• ASAP Leveling
• Queue 0
• For each node
• If Indegree 0
• Level 1
• Queue.Add
• End If
• End For
• While Queue is not empty do
• For each Fanout
• Indegree--
• If Indegree 0 then
• Level(I) Level (I-1) 1
• Queue.Add
• Endif
• End For
• End While

Level-Based Partitioning j 0 While level lt
max_level for each node with level
node.level total_cost node.size RCOST
if((area_filled total_cost)lt freespace
node.partition j area_filled
area_filled total_cost else j
area_filled total_cost Endif
Endfor Endwhile
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Placement Algorithm

• Constructive Deterministic placement
• Places the first node to the right of the parent
• Places the second node on top of the parent
• Similar to what COOL does

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Future work

• To think up a sexy name!
• Testing the system with the ISPD98 Benchmark
  suite
• Complete a 2 stage router
• Methods for handling inter- partition
  communication
• Possible developed for use with real circuit
  formats (XNF, Netlist)

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Conclusion

• For FPGAs to become mainstream an appropriate OS
  must be developed
• Willing to trade the lose in performance for an
  increase in ease of use
• The OS will integrate all of the run-time design
  procedures