CPUs

1
CPUs

• CPU power consumption

2
CPU power consumption

• Most modern CPUs are designed with power
  consumption in mind to some degree
• Power vs. energy
• Power
• P Iavg X Vcc (watt), 1w 1J/s
• The rate at which energy is consumed
• Energy
• 1 Joule 1W X 1s
• Heat-Limited application (HLA)
• heat depends on power consumption
• 600 MHz Alpha 109.0 W _at_ 2.30V Vdd
• Energy-Limited application (ELA)
• battery life depends on energy consumption

3
Power reduction techniques

• Power breakdown in a high-performance CPU

4
Power reduction techniques

• Circuit Level
• Voltage scaling
• Clock gating
• System Level
• Power saving modes
• Cache organization
• Software Based
• Instruction level power analysis

5
CMOS power consumption

• Voltage drops power consumption proportional to
  V2 PsCLVdd2fs
• Toggling (switching) more activity means more
  power
• Leakage basic circuit characteristics can be
  eliminated by disconnecting power

6
CPU power-saving strategies

• Reduce power supply voltage
• Run at lower clock frequency
• Disable function units with control signals when
  not in use
• Disconnect parts from power supply when not in use

7
Power management styles

• Static power management does not depend on CPU
  activity
• Example user-activated power-down mode
• Dynamic power management based on CPU activity
• Example disabling off function units

8
Application PowerPC 603 energy features

• Provides doze, nap, sleep modes
• Dynamic power management features
• Uses static logic
• Can shut down unused execution units
• Cache organized into subarrays to minimize amount
  of active circuitry

9
PowerPC 603 activity

• Percentage of time units are idle for SPEC
  integer/floating-point
• unit Specint92 Specfp92
• D cache 29 28
• I cache 29 17
• load/store 35 17
• fixed-point 38 76
• floating-point 99 30
• system register 89 97

10
Power-down costs

• Going into a power-down mode costs
• time
• energy
• Must determine if going into mode is worthwhile
• Can model CPU power states with power state
  machine

11
Power vs. time running a real application

• Pentium processor

12
Application StrongARM SA-1100 power saving

• Processor takes two supplies
• VDD is main 3.3V supply
• VDDX is 1.5V
• Three power modes
• Run normal operation
• Idle stops CPU clock, with logic still powered
• Sleep shuts off most of chip activity 3 steps,
  each about 30 ms wakeup takes gt 10 ms

13
SA-1110 Power and Clock supply sources
14
SA-1100 power state machine
Prun 400 mW
run
10 ms
160 ms
90 ms
10 ms
90 ms
idle
sleep
Pidle 50 mW
Psleep 0.16 mW
15
Software Power Minimization

• SW constitutes a major component of systems
• Instruction level power analysis
• Instruction base costs
• Effect of circuit state
• Other inter-instruction effects
• Pipeline stalls
• Cache misses

Reducing power in high-performance
microprocessors, V. Tiwari et al. Instruction
level power analysis and optimization of
software, V. Tiwari et al.
16
Instruction base costs

• 486DX2 300-500 mA
• SPARClite 200-300 mA
• DSP 20-60 mA

17
Effect of circuit state

• Case of the 486DX2
• 5-30 mA while most instructions in the range of
  300-420 mA
• Case of a smaller, more basic processor (DSP)

18
Other Inter-instruction effects

• Case of the 486 DX2
• Pipeline stall cycle
• 250 mA
• Cache miss cycle
• 216 mA

19
Overall Instruction level power model

• Ep Si(Bi x Ni) Si,j(Oi,j x Ni,j) SkEk
• Impact of internal power management
• OR, SHIFT, ADD, or MULTIPLY do not show much of
  the cost variation
• Guarded evaluation
• Turn off the power of the unused modules
  dynamically
• Low power Pentium, PowerPC 603, etc.

20
Software Energy Optimization Techniques

• Reducing Memory Accesses
• 486 DX
• Register operand 300 mA
• Memory read 400 mA

21
Software Energy Optimization Techniques, contd

• Energy cost driven code generation
• Traditional cost criteria
• Either the size or the running time
• Instruction Reordering for Low power
• Limited impact in 486DX and the SPARClite
• Beneficial for the DSP (Why?)
• Processor specific optimizations