Computing Faster without CPUs

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Computing Faster without CPUs

• Scientific Applications on FPGA-based
  Reconfigurable Hypercomputers
• by
• Dr. Olaf Storaasli
• Analytical Computational Methods Branch
• Structures and Materials
• for
• May Seminar, Electronic Systems Branch

Field-Programmable Gate Array
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NASA Research Background
FEA NASTRAN
Viking gt Mars
IPAD Integrated Design
NASA Fellowship Norway
Finite Element Machine Early // Computer
Cray GigaFLOP Award Shuttle SRB
Matrix Equation Solver FORTRAN, C, Java
Lanczos Eigensolver 88x Speedup
Intel Supercomputer Users Board, P6 Award
Symposia Large-Scale Apps. (5)
NASA Software of the Year Award
Creativity Innovation Awards
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Exploring Scientific Applicationson
Reconfigurable Hypercomputers
62K gates/FPGA
6M gates/FPGA
Creativity Innovation
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03
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Computing Faster Without CPUs
GOAL Evaluate FPGA-based Hypercomputer
Potential for NASA Scientific Computations
TEAM Dr. Olaf Storaasli, Principal Investigator
Jarek Sobieski, Robert Singleterry, Dave
Rutishauser, Joe Rehder Garry Qualls
, William Fithian-Harvard,
Siddhartha Krishnamurthy-VT Shaun Foley-MIT,
Cris Kania-GS, Neha Dandawate-GS, Patrick
Butler-VT Kristin Barr-JPMorgan, Robert
Lewis-Morehouse , Vincent Vance-VT
PARTNERS Star Bridge Systems, NSA, USAF, MSFC
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William Fithian (Harvard, Merit Scholar, Oracle
Award)
NASA-NHGS mentorship 00-02
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First Langley Hypercomputers
10 FPGAs each
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FPGA Programming

• User controls gates middle man removed
• Code options
• 1-D Text, sequential FORTRAN-like C-to-Gate,
  VHDL
• parallelism esoteric
• 3-D Graphic, parallel drag drop Viva
• Parallelism inherent
• data flow like analog computer

NASA Hypercomputers
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FPGA New Computing Paradigm
Traditional CPU
Reconfigurable FPGA
Sequential 1 operation/cycle
Parallel Inherent
Fixed gates data types
Dynamic gates data types
Wasteful 99 gates idle/cycle yet all draw
power
Efficient Optimizes gates to task
Gateware VIVA Icons Transports
Software Text - 1D
do i 1, billion c ab end do
392 MFLOPS/64 MHz FPGA 3.92 GFLOPS/10 FPGA
board
26 MFLOPS/250 MHz SGI
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Select-Drag-Drop to Code icon
Primitives
Add new code to library Complex algorithms
drill in
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VIVACustom Chip Design Gateware
What Graphics tool to route FPGAs (VHDL
cumbersome)
How Converts icon-transport gateware to
circuit logic
Why Achieve near-ASIC speed (w/o chip design )
Growth in VIVA Capability
Extensive Data Types Trig, Logs,
Transcendentals File Input/Output Vector-Matrix
Support Access to Multiple FPGAs Extensive
Documentation Stable Development Few bugs
NO Floating Point NO Scientific Functions NO File
Input/Output NO Vector-Matrix Support Access to
One FPGA Primitive Documentation Weekly
Changes Frequent bugs
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Parallel Use of Parallel FPGAs
Windows Server
Control Panel
HC-38m Hypercomputer 7 FPGAs 6M Gates
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Algorithms Developed

• Matrix Algebra V, M, VTV, MxM,GCD,

• n! gt Probability Combinations/Permutations
  AirSC

• Cordic gt Transcendentals sin, log, exp, cosh

• ?y/?x ?f(x)dx gt Runge-Kutta CFD,
  Newmark Beta CSM

• Matrix Equation Solver Ax b - Gauss
  Jacobi

.

• Dynamic Analysis Mü Cu Ku
  NLT P(t)
• Analog Computing digital accuracy

• Nonlinear Analysis Analog simulation
• avoids NLT devpt time

In AIAA Military Aerospace Programmable
Logic Device (MAPLD) papers
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Numeric Integration
Output (Area under curve)
S f(x)Dx
xi1xiDx
Dx
f(x)x2
f(x)Dx
Control
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VIVA Sparse Matrix Equation SolverJacobi
Iterative (3x3 Demo)
Control 3 Row Loads
3 // Dot Products
Axb x1 1/A11(b1 - A12x2 - A13x3)
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Analog Diagram of 2x2 Equations Solution
bz
bz
z
P-bz
x
b
-
input
P
yi (P - b zi-1)/a
/
y
a
- initialized
output y
y
x
d
-
M
zi (M - dyi-1)/e
input
/
z
e
output z
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Fixed-Point Iteration VIVA Diagram
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Year 2 Exploit Latest FPGAs
Rapid Growth in FPGA Capability
FPGA (Feb 01) FPGA (Oct 02)
Plans - Millions of Matrix Equations
Structures, Electromagnetics Acoustics -
Rapid Static Dynamic Structural Analyses -
Cray Vector Computations in Weather Code (VT
PhD) - Robert on Administrators Fellowship at
Star Bridge Systems - Simulate advanced
computing concepts using VIVA - Collaborate
with SBS, NSA, AT to expand VIVA libraries -
Tailor VIVA development for NASA applications -
Target applications to NASA programs (e.g. EDB
Collaboration??)
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SummaryWhat Were Learning
We like FPGA promise accomplished much
Hardware Testing 3 futuristic FPGA systems
FPGAs Inherently //, flexible, efficient,
fast, dramatic advances
VIVA Powerful growing (tailor to NASA needs)
Applications 02 - Diverse pathfinder
algorithms developed
03 - Comprehensive NASA engineering
applications
Speed Year 1 4 GFLOPS gt Year 2 329 GFLOPS
Future exploit capability on NASA cutting edge
innovations
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Langley Reconfigurable Computing Research

• 1. Singleterry, Robert C., Jaroslav
  Sobieszczanski-Sobieski, and Samuel Brown.
  Field-Programmable Gate Array Computer in
  Structural Analysis an Initial Exploration.
  43rd American Institute of Aeronautics and
  Astronautics (AIAA) Structures, Structural
  Dynamics, and Materials Conference. April 22-25,
  2002. 
• 2. Storaasli, Olaf O., Robert C. Singleterry,
  and Samuel Brown. Scientific Computations on a
  NASA Reconfigurable Hypercomputer. Abstract
  accepted for 5th Military and Aerospace
  Programmable Logic Devices (MAPLD) Conference,
  Paper in preparation. September 10-12, 2002.
• 3. Fithian, William, Samuel Brown, and Tyler
  Reed. Object Synchronization in VIVA 1.5.
  Briefing prepared for VIVA users at NASA
  Marshall, Eglin AFB, Progress Forge, Inc., and
  Star Bridge Systems, Inc. March 26, 2002.
• 4. Barr, Kristen, Shaun Foley, and Robert A.
  Lewis II. Hypercomputing with the CORDIC
  Algorithm. August, 2001. Presentation of
  research conducted under Dr. Olaf O. Storaasli,
  June-August, 2001.
• 5. Butler, Patrick. New Horizons Governors
  School Mentorship Project. May, 2001.
  Presentation of research conducted under Dr. Olaf
  O. Storaasli, September 2000 May 2001.
• 6.  Dandawate, Neha. Reckless Speeding The
  Investigation of the Programming Capabilities of
  the HAL Hypercomputer. July, 2002. Presentation
  of research conducted under Dr. Olaf O.
  Storaasli, June July, 2002.
• 7. Dandawate, Neha. The Investigation of the
  Programming Capabilities of the HAL-15
  Hypercomputer. July, 2002. Paper on research
  conducted under Dr. Olaf O. Storaasli, June
  July, 2002.
• 8. Fithian, William. Developing a Matrix
  Equation Solver for the HAL-15 Hypercomputer.
  December, 2001. Proposal for research to be
  conducted under Dr. Olaf O. Storaasli, September
  2001 May 2002.
• 9. Fithian, William. Developing a Matrix
  Equation Solver for the HAL-15. May, 2002.
  Presentation of research conducted under Dr. Olaf
  O. Storaasli, September 2001 May 2002.
• 10. Fithian, William. Jacobi Iterative Matrix
  Equation Solver for Star Bridge Systems FPGA
  Hypercomputer. September, 2002. In preparation.
• 11. Foley, Shaun. Scientific Hypercomputing.
  August, 2001. Paper describing research
  conducted under Dr. Olaf O. Storaasli, June
  August, 2001.
• 12. Krishnamurthy, Siddhartha. Development of
  an Integration Algorithm for Field Programable
  Gate Arrays using VIVA. July, 2002. Paper
  describing research conducted under Dr. Robert C.
  Singleterry, June Aug 2002.  
• Further Information Google
  olaf acmb