Virtual Memory

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Virtual Memory
CS147 Lecture 14

• Prof. Sin-Min Lee
• Department of Computer Science

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Given the following implementation using a 3?8
decoder with negated outputs, what is the
function K(A,B,C)?
a. K(A,B,C) A.B' A'.B.C b. K(A,B,C) A.B
A'.B' A'.C' c. K(A,B,C) (A B' C').(A' B
C).(A' B C') d. K(A,B,C) 1 e. K(A,B,C) 0
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2x4 Decoder
J K
Q
X
Q
Y Z
CLK
000,001,010,011,110,111
000,001,010,100,101,110
100,101
0
1
011,111
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FSM
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Find the Boolean expression for JA, KA, DB and Z

• JA X'QBQA QBQA
• KA X' QB
• DB QB'QA QB QA QB
• Z X'QBQA

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Find the Boolean expression for the next states
QA and QB.

• QB DB QA QB
• For J-K Flip Flop, we have QA JAQA' KA'QA
• Hence, QA (X'QBQA QBQA')QA' (X'QB)'QA 0
  QBQA' (X.QB")QA QBQA' XQB'QA

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Transition Table
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State Diagram
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Where can a block be placed in Cache? (2)

• Direct mapped Cache
• Each block has only one place where it can appear
  in the cache
• (Block Address) MOD (Number of blocks in cache)
• Fully associative Cache
• A block can be placed anywhere in the cache
• Set associative Cache
• A block can be placed in a restricted set of
  places into the cache
• A set is a group of blocks into the cache
• (Block Address) MOD (Number of sets in the cache)
• If there are n blocks in the cache, the placement
  is said to be n-way set associative

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Which Block should be Replaced on a Cache Miss?

• When a miss occurs, the cache controller must
  select a block to be replaced with the desired
  data
• Benefit of direct mapping is that the hardware
  decision is much simplified
• Two primary strategies for full and set
  associative caches
• Random candidate blocks are randomly selected
• Some systems generate pseudo random block
  numbers, to get reproducible behavior useful for
  debugging
• LRU (Last Recently Used) to reduce the chance
  that information that has been recently used will
  be needed again, the block replaced is the
  least-recently used one.
• Accesses to blocks are recorded to be able to
  implement LRU

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The connection between the CPU and cache is very
fast the connection between the CPU and memory
is slower
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There are three methods in block placement
Direct mapped if each block has only one place
it can appear in the cache, the cache is said to
be direct mapped. The mapping is usually (Block
address) MOD (Number of blocks in cache) Fully
Associative if a block can be placed anywhere
in the cache, the cache is said to be fully
associative. Set associative if a block can
be placed in a restricted set of places in the
cache, the cache is said to be set associative .
A set is a group of blocks in the cache. A block
is first mapped onto a set, and then the block
can be placed anywhere within that set. The set
is usually chosen by bit selection that is,
(Block address) MOD (Number of sets in cache)
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• Direct mapped cache A block from main memory can
  go in exactly one place in the cache. This is
  called direct mapped because there is direct
  mapping from any block address in memory to a
  single location in the cache.

cache
Main memory
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• Fully associative cache A block from main
  memory can be placed in any location in the
  cache. This is called fully associative because a
  block in main memory may be associated with any
  entry in the cache.

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Memory/Cache Related Terms

• Set associative cache The middle range of
  designs between direct mapped cache and fully
  associative cache is called set-associative
  cache. In a n-way set-associative cache a block
  from main memory can go into n (n at least 2)
  locations in the cache.

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Replacing Data

• Initially all valid bits are set to 0
• As instructions and data are fetched from memory,
  the cache is filling and some data need to be
  replaced.
• Which ones?
• Direct mapping obvious

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Replacement Policies for Associative Cache

• FIFO - fills from top to bottom and goes back to
  top. (May store data in physical memory before
  replacing it)
• LRU replaces the least recently used data.
  Requires a counter.
• Random

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Replacement in Set-Associative Cache

• Which if n ways within the location to replace?
• FIFO
• Random
• LRU

Accessed locations are D, E, A
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Cache Performance

• Cache hits and cache misses.
• Hit ratio is the percentage of memory accesses
  that are served from the cache
• Average memory access time
• TM h TC (1- h)TP

Tc 10 ns Tp 60 ns
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Associative Cache

• Access order
• A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 V0 G3 C2
  H7 I6 A0 B0

FIFO h 0.389 TM 40.56 ns
Tc 10 ns Tp 60 ns
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Direct-Mapped Cache

• Access order
• A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 V0 G3 C2
  H7 I6 A0 B0

h 0.167 TM 50.67 ns
Tc 10 ns Tp 60 ns
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2-Way Set Associative Cache

• Access order
• A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 V0 G3 C2
  H7 I6 A0 B0

LRU h 0.31389 TM 40.56 ns
Tc 10 ns Tp 60 ns
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Associative Cache(FIFO Replacement Policy)
A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 B0
G3 C2 H7 I6 A0 B0
Hit ratio 7/18
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Two-way set associative cache(LRU Replacement
Policy)
A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 B0
G3 C2 H7 I6 A0 B0
Hit ratio 7/18
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Associative Cache with 2 byte line size (FIFO
Replacement Policy)
A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 B0
G3 C2 H7 I6 A0 B0 A and J B and D C and
G E and F and I and H
Hit ratio 11/18
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Direct-mapped Cachewith line size of 2 bytes
A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 B0
G3 C2 H7 I6 A0 B0 A and J B and D C and
G E and F and I and H
Hit ratio 7/18
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Two-way set Associative Cachewith line size of 2
bytes
A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 B0
G3 C2 H7 I6 A0 B0 A and J B and D C and
G E and F and I and H
Hit ratio 12/18
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Page Replacement - FIFO

• FIFO is simple to implement
• When page in, place page id on end of list
• Evict page at head of list
• Might be good? Page to be evicted has been in
  memory the longest time
• But?
• Maybe it is being used
• We just dont know
• FIFO suffers from Beladys Anomaly fault rate
  may increase when there is more physical memory!

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• Parkinson's law "Programs expand to fill the
  memory available to hold them"
• Idea Manage the storage available efficiently
  between the available programs.

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Before VM

• Programmers tried to shrink programs to fit tiny
  memories
• Result
• Small
• Inefficient Algorithms

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Solution to Memory Constraints

• Use a secondary memory such as disk
• Divide disk into pieces that fit memory (RAM)
• Called Virtual Memory

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Implementations of VM

• Paging
• Disk broken up into regular sized pages
• Segmentation
• Disk broken up into variable sized segments

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Memory Issues

• Idea Separate concepts of
• address space Disk
• memory locations RAM
• Example
• Address Field 216 65536 memory cells
• Memory Size 4096 memory cells

How can we fit the Address Space into Main Memory?
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Paging

• Break memories into Pages
• NOTE normally Main Memory has thousands of pages

1 page 4096 bytes
page
page
page
New Issue How to manage addressing?
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Address Mapping
Mapping 2ndary Memory addresses to Main Memory
addresses
1 page 4096 bytes
page
page
page
physical address
virtual address
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Address Mapping
Mapping 2ndary Memory (program/virtual) addresses
to Main Memory (physical) addresses
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Paging
virtual
physical

• Illusion that Main Memory is
• Large
• Contiguous
• Linear
• Size(MM) Size(2ndry M)
• Transparent to Programmer

4095
8191
0
4096
4095 / 0
4095 / 0
page
0
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Paging Implementation

• Virtual Address Space (Program) Physical
  Address Space (MM)
• Broken up into equal pages
• (just like cache MM!!)
• Page size ? Always a power of 2
• Common Size
• 512 to 64K bytes

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Paging Implementation

• Page Frames
• Page Tables
• Programs use Virtual Addresses

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Memory Mapping

• Page Frame
• home of VM pages in MM
• Page Table
• home of mappings for VM pages

Page
Page Frame
Note 2ndry Mem 64K Main Mem 32K
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Memory Mapping

• Memory Management Unit (MMU)
• Device that performs virtual-to-physical
  mapping

MMU
32-bit VM Address
MMU
15-bit Physical Address
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Memory Management Unit
MMU

• 32-bit Virtual Address
• Broken into 2 portions
• 20-bit 12-bit
• Virtual page offset in page
• (since our pages are 4KB)
• How to determine if page is in MM?
• Present/Absent Bit
• in Page Table Entry

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Demand Paging
Page Fault Requested page is not in
MM Demand Paging Page is demanded by
program Page is loaded into MM
Possible Mapping of pages
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Demand Paging
But What to bring in for a program on start up?
Page Fault Requested page is not in
MM Demand Paging Page is demanded by
program Page is loaded into MM
Possible Mapping of pages
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Working Set

• Set of pages used by a process
• Each process has a unique memory map
• Importance in regards to a multi-tasked OS
• At time t, there is a set of
  all k recently used pages
• References tend to cluster on a small number of
  pages

Put this set to Work!!! Store Load it during
Process Switching
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Page Replacement Policy

• Working Set
• Set of pages used actively heavily
• Kept in memory to reduce Page Faults
• Set is found/maintained dynamically by OS
• Replacement OS tries to predict which page would
  have least impact on the running program

Common Replacement Schemes Least Recently Used
(LRU) First-In-First-Out (FIFO)
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Replacement Policy

• Placement Policy
• Which page is replaced?
• Page removed should be the page least likely to
  be referenced in the near future
• Most policies predict the future behavior on the
  basis of past behavior

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Replacement Policy

• Frame Locking
• If frame is locked, it may not be replaced
• Kernel of the operating system
• Control structures
• I/O buffers
• Associate a lock bit with each frame

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Basic Replacement Algorithms

• Optimal policy
• Selects for replacement that page for which the
  time to the next reference is the longest
• Impossible to have perfect knowledge of future
  events

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Basic Replacement Algorithms

• Least Recently Used (LRU)
• Replaces the page that has not been referenced
  for the longest time
• By the principle of locality, this should be the
  page least likely to be referenced in the near
  future
• Each page could be tagged with the time of last
  reference. This would require a great deal of
  overhead.

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Basic Replacement Algorithms

• First-in, first-out (FIFO)
• Treats page frames allocated to a process as a
  circular buffer
• Pages are removed in round-robin style
• Simplest replacement policy to implement
• Page that has been in memory the longest is
  replaced
• These pages may be needed again very soon

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Basic Replacement Algorithms

• Clock Policy
• Additional bit called a use bit
• When a page is first loaded in memory, the use
  bit is set to 1
• When the page is referenced, the use bit is set
  to 1
• When it is time to replace a page, the first
  frame encountered with the use bit set to 0 is
  replaced.
• During the search for replacement, each use bit
  set to 1 is changed to 0

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Page Replacement Policies

• Upon Replacement
• Need to know whether to write data back
• Add a Dirty-Bit
• Dirty Bit 0 Page is clean No writing
• Dirty Bit 1 Page is dirty Write back