HCAL Data Concentrator

1
HCAL Data Concentrator

• Readout Unit Working Group
• DCC Status Report
• E. Hazen, J. Rohlf, S.X.Wu
• Boston University

2
Data Concentrator Card

• Review of Functionality
• Receive 1 block per L1A from up to 15 HTRs
• Add header and trailer, send to DAQ using66MHz
  S-Link64
• Check for synchronization and other errors
• Report errors and pending overflows viaaTTS
  interface
• Provide VME access for spy and trigger data stream

sTTS
3
DCC Configuration
Two VME slots (3-layer board stack) All I/O on
front panel
S-Link64
DAQ S-Link
S-Link
VME
sTTS
TTC
DCC Logic Mezzanine Card
15 HTR INPUTS
Spare
235 pin 2mm Connector
PC-MIP Link Receivers
4
HCAL Data Concentrator Card

• Sub-Assembly Status
• VME 9Ux400mm motherboard with PCI buses
• Production Completed
• 3-channel PCI-based Link Receiver Board
• Production Completed
• Logic mezzanine board
• Two prototype versions built, used for testbeam
  2002
• Minor design changes remain to accommodate
  S-Link64

5
DCC Prototype Photograph
S-Link64 Site
Link Receivers
Logic Board (prototype shown)
VME Motherboard
6
DCC Technical Issues

• S-Link64 not a problem
• Our logic board layout must change anyhow, so we
  will use a larger FPGA with 64 bits output _at_
  66MHz
• VME64x compatibility
• Will accommodate standard as far as possible.
• Per discussions with Christophe S., HAL may be
  modified to directly support heirarchial hardware
  such as the DCC.
• TTCRx Integration
• Decided to use electrical fanout of TTC signals,
  received with new TTCRx mezzanine board(same
  board used for HTR)

7
DCC Schedule