Prabhat Mishra

1
Functional Verification of Pipelined Processors A
Case Study

• Prabhat Mishra
• Computer and Information Science and Engineering
• University of Florida
• Nikil Dutt
  Yaron Kashai
• Center for Embedded Computer Systems
  Verisity Design, Inc.
• University of California, Irvine
  MountainView, CA

2
Outline

• Functional Verification
• A Challenge
• Test Generation and Coverage Estimation
  Framework
• Pipelined Processors
• A Case Study
• VLIW DLX Processor
• Summary

3
Functional Verification of SOC Designs
2000
1000B
2007
200
10B
2001
Engineer Years
Simulation Vectors
100M
20
1995
100M
1M
10M
Logic Gates
Source Synopsys
71 of SOC re-spins are due to logic bugs
Source G. Spirakis, keynote address at DATE 2004
4
Functional Verification of Microprocessors

• Functional verification is a major bottleneck
• Number of logic bugs is increasing at 3-4 times /
  generation

5
Pentium 4 Bugs Breakdown
Source Bob Bentley, HLDVT 2002
Micro-architectural complexity is a major
contributor
6
Bottlenecks of Functional Verification

• Lack of high-level models
• Captures micro-architectural details
• Enables early functional validation
• Lack of functional coverage metric
• Code coverage, FSM coverage, not sufficient
• A case study for functional verification of
  pipelined processors
• Specification-driven test generation and
  coverage estimation using Specman Elite

7
Related Work

• Directed test program generation
• Aharon et al., DAC 1995, Shen et al., DAC 1999
• Test generation for pipelined processors
• Ur and Yadin, DAC 1999
• Iwashita et al., ICCAD 1994
• Campenhout et al., DAC 1999
• No coverage metric for pipeline interactions
• Functional test program generation
• Chen et al., DAC03, Lai and Cheng, DAC01
• Thatte et al., IEEE Computers, 1980
• Applied in the context of manufacturing testing

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Outline

• Motivation
• Functional Verification Framework
• A Case Study
• Summary

9
Functional Verification of Pipelined Processors
Test Generator
Pipelined Processor
TestGen
MOV R1, 011 MOV R2, 010 ADD R3, R1, R2 R3 101
Test Program
R3 101 ?
Check Result
Verify the functionality of the processor using
assembly programs
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Test Generation and Coverage Estimation
Architecture Specification (ADL Description)
ISA Specification (e Description)
Coverage Specification
Pipelined Implementation (e Description)
Coverage Estimation
Simulator
Random
Test Generation
Specman Elite
Directed
External Test Programs
11
Outline

• Motivation
• Functional Verification Framework
• Architecture Specification
• e Model Generation
• Test Generation
• Coverage Estimation
• Summary

12
Architecture Specification

• Capture micro-architecture details
• Structure
• Components, connectivity,
• Behavior
• Instruction-set (ISA)
• Using Architecture Description Language
• EXPRESSION ADL
• Developed at UC, Irvine

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Specification of the DLX Processor
PC
Memory
Fetch
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
FADD3
FADD4
MUL7
MEM
WriteBack
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Specification of the DLX Processor
PC
Memory
Fetch
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
FADD3
FADD4
MUL7
MEM
WriteBack
15
Specification of the DLX Processor
PC
Memory
Fetch
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
FADD3
FADD4
MUL7
MEM
WriteBack
16
Specification of the DLX Processor
PC
Memory
Fetch
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
FADD3
FADD4
MUL7
MEM
WriteBack
17
Specification of the DLX Processor
PC
Memory
Fetch
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
FADD3
FADD4
MUL7
MEM
WriteBack
18
Specification of the DLX Processor
PC
Memory
Fetch
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
FADD3
FADD4
MUL7
MEM
WriteBack
19
Specification of the DLX Processor
Structure
PC
Memory
Fetch
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
Behavior
(OPCODE ADD (OPERANDS (SRC1 rf) (SRC2 imm)
(DEST rf)) (BEHAVIOR DEST SRC1 SRC2)
(FORMAT ) )
FADD3
FADD4
MUL7
MEM
WriteBack
20
Specification of the DLX Processor
Structure
PC
Memory
Fetch
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
Behavior
Mapping
(OPCODE ADD (OPERANDS (SRC1 rf) (SRC2 imm)
(DEST rf)) (BEHAVIOR DEST SRC1 SRC2)
(FORMAT ) )
FADD3
FADD4
MUL7
MEM
WriteBack
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Outline

• Motivation
• Functional Verification Framework
• Architecture Specification
• e Model Generation
• Test Generation
• Coverage Estimation
• Summary

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Model Generation

• Generating executable models from the ADL
  specification
• Instruction-set (ISA) models
• using behavioral description
• Pipelined implementation
• using functional abstraction (ISSS 2001)
• Generation of coverage specification
• based on functional fault models

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Instruction-Set Models

• type opcodes
• LB, SB, , ADDI, SUBI, // I-type opcodes
• ADD, SUB, MULT, // R-type opcodes
• J, JAL, TRAP, RFE, // J-type opcodes
• type registers R0, R1, R2, R31
• type immediate int (bits 16)
• struct instructions
• opcode opcodes
• when I_type instructions
• src1 cpu_reg_t dest
  registers src2 immediate
• when R_type instructions
• src1 cpu_reg_t src2
  registers dest registers
• when J_type instructions src1
  offset

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Functional Coverage Specification

• Register Read/Write
• All registers are written and read.
• Operation Execution
• All operations are executable.
• Pipeline Execution
• All pipeline interactions are activated.

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Test Generation

• Generated test programs in three ways
• Random
• Constrained-random
• Manual
• Specman Elite is used to generate random and
  constrained-random test vectors
• Manual tests are used improve functional
  coverage.

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Test Generation

• Random
• Modification of a variable decides the number of
  tests to generate.
• Constrained-random
• Several constraints are used to generate
  directed tests
• For example, to generate tests for register
  read/write, R-type operations are used.
• R-type 3 register operands
• I-type 2 register operands
• J-type 0 register operands

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VALIDATION
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Coverage Estimation

• Instruction definition is used
• opcode, dest, src1, src2
• Register read/write
• coverage of src1 and src2 indicates reads.
• coverage dest indicates writes.
• Operation execution
• coverage of opcode field
• Pipeline execution
• use variable for each stall/exception
• cross-coverage is used to estimate coverage of
  multiple exception scenarios.

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Test Generation Results
Fault Models Test Generation Techniques Test Generation Techniques Test Generation Techniques
Fault Models Random Constrained Manual
Register Read/Write 3900 750 130
Operation Execution 437 443 182
Pipeline Execution 30000 (25) 30000 (30) 626 (100)
Random or constrained-random techniques could not
activate any multiple exceptions scenarios
- Low coverage in pipeline execution
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The Framework is Available

• Test generation and coverage estimation
  framework for VLIW DLX is available
• https//www.verificationvault.com
• It includes
• VLIW DLX models
• e specification for reference (ISA model)
• pipelined implementation in e.
• Components for random/directed test generation
  and incorporation of external tests
• Components for data/temporal checking and
  coverage estimation.

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Summary

• Functional verification is a challenge
• Presented a case study of validation of
  pipelined processor using Specman Elite
• Architecture specification using ADL
• e model generation
• Test program generation
• Functional coverage estimation
• Future work
• Development of functional fault models
• Functional coverage-driven test generation

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• Thanks!