VLSI Arithmetic Adders

1
VLSI ArithmeticAdders Multipliers

• Prof. Vojin G. Oklobdzija
• University of California
• http//www.ece.ucdavis.edu/acsel

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Introduction

• Digital Computer Arithmetic belongs to Computer
  Architecture, however, it is also an aspect of
  logic design.
• The objective of Computer Arithmetic is to
  develop appropriate algorithms that are utilizing
  available hardware in the most efficient way.
• Ultimately, speed, power and chip area are the
  most often used measures, making a strong link
  between the algorithms and technology of
  implementation.

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Basic Operations

• Addition
• Multiplication
• Multiply-Add
• Division
• Evaluation of Functions
• Multi-Media

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Addition of Binary Numbers
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Addition of Binary Numbers
Full Adder. The full adder is the fundamental
building block of most arithmetic circuits
  The sum and carry outputs are described
as
ai
bi
Full Adder
Cin
Cout
si
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Addition of Binary Numbers
Propagate
Generate
Propagate
Generate
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Full-Adder Implementation

• Full Adder operations is defined by equations

Carry-Propagate and Carry-Generate gi
One-bit adder could be implemented as shown
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High-Speed Addition
One-bit adder could be implemented more
efficiently because MUX is faster
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The Ripple-Carry Adder
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The Ripple-Carry Adder
From Rabaey
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Inversion Property
From Rabaey
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Minimize Critical Path by Reducing Inverting
Stages
From Rabaey
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Ripple Carry Adder

• Carry-Chain of an RCA implemented using
  multiplexer from the standard cell library

Critical Path
Oklobdzija, ISCAS88
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Manchester Carry-Chain Realization of the Carry
Path

• Simple and very popular scheme for implementation
  of carry signal path

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Original Design
T. Kilburn, D. B. G. Edwards, D. Aspinall,
"Parallel Addition in Digital Computers A New
Fast "Carry" Circuit", Proceedings of IEE, Vol.
106, pt. B, p. 464, September 1959.
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Manchester Carry Chain (CMOS)

• Implement P with pass-transistors
• Implement G with pull-up, kill (delete) with
  pull-down
• Use dynamic logic to reduce the complexity and
  speed up

Kilburn, et al, IEE Proc, 1959.
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Pass-Transistor Realization in DPL
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Carry-Skip Adder
MacSorley, Proc IRE 1/61 Lehman, Burla, IRE Trans
on Comp, 12/61
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Carry-Skip Adder
Bypass
From Rabaey
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Carry-Skip Adder N-bits, k-bits/group, rN/k
groups
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Carry-Skip Adder
k
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Variable Block Adder(Oklobdzija, Barnes IBM
1985)
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Carry-chain of a 32-bit Variable Block
Adder(Oklobdzija, Barnes IBM 1985)
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Carry-chain of a 32-bit Variable Block
Adder(Oklobdzija, Barnes IBM 1985)
6
5
5
4
4
3
3
D9
1
1
Any-point-to-any-point delay 9 D as compared
to 12 D for CSKA
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Carry-chain block size determination for a 32-bit
Variable Block Adder(Oklobdzija, Barnes IBM
1985)
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Delay Calculation for Variable Block
Adder(Oklobdzija, Barnes IBM 1985)
Delay model
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Variable Block Adder(Oklobdzija, Barnes IBM
1985)
Variable Group Length
Oklobdzija, Barnes, Arith85
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Carry-chain of a 32-bit Variable Block
Adder(Oklobdzija, Barnes IBM 1985)
Variable Block Lengths

• No closed form solution for delay
• It is a dynamic programming problem

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Delay Comparison Variable Block
Adder(Oklobdzija, Barnes IBM 1985)
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Delay Comparison Variable Block Adder
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