Development and Verification of DSP Macros

1
Development and Verification of DSP Macros

• Focusing on an FFT Algorithm
• Adam Miller

2
Overview

• Background
• Development
• Functionality
• Specifications
• Flexibility
• Verification
• Test Vector Creation
• Simulations

3
Background

• Digital Signal Processing
• Time Domain/Frequency Domain
• Fast Fourier Transform
• Design for Reuse
• Development Time
• Flexible Code

4
Functionality

• FFT
• Radix 22SDF Algorithm
• Single Path
• Serial Input/Output
• Natural Order Input
• Bit-Reversed Output
• IFFT Capability

5
Specifications

• Provided by Boeing
• Different Versions
• NR-FFT64 Not Reconfigurable, 64 point FFT
• FFT Reconfigurable FFT

6
Flexibility

• Parameters
• Input Width 2 to 34 bits
• Number of Points 4 to 1024
• Adder Growth 0 or 1 bit
• Twiddle Width 2 to 24 bits
• Multiplier Growth 1 to Twiddle Width1
• Twiddle Factor Generation

7
Test Vector Creation

• MATLAB
• Pros
• Code modification
• Built in DSP and Graphing capabilities
• Easy to use
• Cons
• Slower run times
• Not Bit True
• Test Vector Description

8
Simulations

• Testbench
• ModelSim
• Pre-Synthesis
• Pre-Layout
• Post Layout
• Visual Confirmation
• BIST