Title: Arithmetic
1Arithmetic Circuits
2A Generic Digital Processor
3Building Blocks for Digital Architectures
Arithmetic unit
Bit-sliced datapath
(adder, multiplier, shifter, comparator, etc.)
-
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
4An Intel Microprocessor
Itanium has 6 integer execution units like this
5Bit-Sliced Design
6Bit-Sliced Datapath
7Itanium Integer Datapath
Fetzer, Orton, ISSCC02
8Adders
9Full-Adder
10The Binary Adder
11Express Sum and Carry as a function of P, G, D
Define 3 new variable which ONLY depend on A, B
Generate (G) AB
Propagate (P) A
B
Å
Delete/kill
A
B
S
C
D and P
Can also derive expressions for
and
based on
o
Note that we will be sometimes using an alternate
definition for
Propagate (P) A
B
12The Ripple-Carry Adder
Worst case delay linear with the number of bits
td O(N)
tadder (N-1)tcarry tsum
Goal Make the fastest possible carry path circuit
13Complimentary Static CMOS Full Adder
28 Transistors
14Inversion Property
15Minimize Critical Path by Reducing Inverting
Stages
Exploit Inversion Property
16A Better Structure The Mirror Adder
17Mirror Adder
Stick Diagram
18The Mirror Adder
- The NMOS and PMOS chains are completely
symmetrical. A maximum of two series transistors
can be observed in the carry-generation
circuitry. - When laying out the cell, the most critical issue
is the minimization of the capacitance at node
Co. The reduction of the diffusion capacitances
is particularly important. - The capacitance at node Co is composed of four
diffusion capacitances, two internal gate
capacitances, and six gate capacitances in the
connecting adder cell . - The transistors connected to Ci are placed
closest to the output. - Only the transistors in the carry stage have to
be optimized for optimal speed. All transistors
in the sum stage can be minimal size.
19Transmission Gate Full Adder
20Manchester Carry Chain
21Manchester Carry Chain
22Manchester Carry Chain
Stick Diagram
23Carry-Skip Adder
Also called Carry-bypass
24Carry-Skip Adder (cont.)
tadder tsetup Mtcarry (N/M-1)tbypass
(M-1)tcarry tsum
25Carry Ripple versus Carry Bypass
26Carry-Select Adder
27Carry Select Adder Critical Path
28Linear Carry Select
29Square Root Carry Select
30Adder Delays - Comparison
31LookAhead - Basic Idea
32Look-Ahead Topology
Expanding Lookahead equations
All the way
33Logarithmic Look-Ahead Adder
34Carry Lookahead Trees
Can continue building the tree hierarchically.
35Tree Adders
16-bit radix-2 Kogge-Stone tree
36Tree Adders
16-bit radix-4 Kogge-Stone Tree
37Sparse Trees
16-bit radix-2 sparse tree with sparseness of 2
38Tree Adders
Brent-Kung Tree
39Example Domino Adder
Propagate
Generate
40Example Domino Adder
Propagate
Generate
41Example Domino Sum
42Multipliers
43The Binary Multiplication
44The Binary Multiplication
45The Array Multiplier
46The MxN Array Multiplier Critical Path
Critical Path 1 2
47Carry-Save Multiplier
48Multiplier Floorplan
49Wallace-Tree Multiplier
50Wallace-Tree Multiplier
51Wallace-Tree Multiplier
52Multipliers Summary
53Shifters
54The Binary Shifter
55The Barrel Shifter
Area Dominated by Wiring
564x4 barrel shifter
Widthbarrel 2 pm M
57Logarithmic Shifter
580-7 bit Logarithmic Shifter
A
3
Out3
A
2
Out2
A
1
Out1
A
0
Out0