ECE 444

1
ECE 444

• Session 10
• Dr. John G. Weber
• KL-241E
• 229-3182
• John.Weber_at_notes.udayton.edu
• jweber-1_at_woh.rr.com

2
Serial Data Transmission

• RS- 232
• Standard Serial Ports for PC
• Interfaces based on devices called UARTs
• Universal Asynchronous Receiver Transmitter
• Asynchronous Communication
• Each character sent asynchronously
• Receiver must detect the beginning and end of
  each character
• Rates are relatively slow (300, 600, 1200, 2400,
  4800, 9600, 14400, 28800, etc.)

3
Signal Definition

• Start Bit
• High for one bit time
• Data Bits
• Transmitted LSB first
• Characters usually transmitted in 7-bit ASCII
  format
• Eighth data bit is a parity bit
• Stop Bit
• Low for at least one bit time
• Rest State
• State of signal between characters
• Low

4
PC Comm Port Signal Levels

• Voltage Levels are 12.5 V and 12.5 V
• Rest State is 12.5 V
• Logic 1 is 12.5 V
• Logic 0 is 12.5 V

5
UART Receiver Architecture
6
Signal Detection and Synchronization
7
Example Receiver Design

• Page 394 in Text
• Assumes that sample clock is 8 times the
  frequency of the bit clock
• Typical differences are an order of magnitude
  more
• Implies that start bit sample size is four

8
Example Receiver Verilog Code
// uart_rcvr.v // An 8-bit uart receiver module
based on Ciletti module uart_rcvr (RCV_datareg,
read_not_ready_out,Error1, Error2, Serial_in,
read_not_ready_in, Sample_clk, reset_) //sample
clock is 8 times bit clock (Bit_clk) parameter wor
d_size 8 parameter half_word
word_size/2 parameter Num_counter_bits 4 //mus
t hold count of word_size parameter Num_state_bits
2 //Number of bits in state parameter idle 2
'b00 //Encode idle state parameter starting 2'
b01 //Encode starting state parameter receiving
2'b10 //Encode receiving state   output word_
size-10 RCV_datareg //Declare
outputs output read_not_ready_out, Error1,
Error2 input Serial_in, //Declare
inputs Sample_clk, reset_, read_not_ready_in
reg inc_Bit_counter, //Declare all one-bit
registers clr_Bit_counter, inc_Sample_counter,
clr_Sample_counter, shift, load, read_not_ready
_out, Error1, Error2   reg word_size-10 RCV_
datareg, RCV_shiftreg reg Num_counter_bits-1
0 Sample_counter //Works for the 81
relationship // between sample clock and
bit clock reg Num_counter_bits0 Bit_counter r
eg Num_state_bits-10 state, next_state
9
Example Verilog UART Receiver (Cont)
//Combinatorial logic for next state and
conditional outputs always _at_(state or Serial_in
or read_not_ready_in or Sample_counter or
Bit_counter) begin read_not_ready_out
0 inc_Bit_counter 0 clr_Bit_counter
0 inc_Sample_counter 0 clr_Sample_counter
0 shift 0 load 0 Error1
0 Error2 0 next_state state
10
Example Verilog UART Receiver (Cont)
case (state) idle if (Serial_in 0)
next_state starting //detects the start
bit starting if (Serial_in
1) begin next_state idle clr_Samp
le_counter 1 end else if
(Sample_counter half_word -1) // counts
samples equal to ½ word time begin next
_state receiving clr_Sample_counter
1 end else inc_Sample_counter
1 receiving if (Sample_counter lt
word_size -1) //counts samples equal to one word
time inc_Sample_counter 1 else beg
in clr_Sample_counter 1 if
(Bit_counter ! word_size) begin sh
ift 1 inc_Bit_counter
1 end else begin next_stat
e idle read_not_ready_out
1 clr_Bit_counter 1 if
(read_not_ready_in 1) Error1
1 else if (Serial_in 0) Error2
1 else load 1 end end
default next_state idle endcase end
11
Example Verilog UART Receiver (Cont)
//state transitions and register
transfers always _at_(posedge Sample_clk) begin
if (reset_ 0) begin state lt
idle Sample_counter lt 0 Bit_counter
lt 0 RCV_datareg lt 0 RCV_shiftreg lt
0 end else begin state lt
next_state if (clr_Sample_counter
1) Sample_counter lt 0 else if
(inc_Sample_counter 1) Sample_counter lt
Sample_counter 1 if (clr_Bit_counter
1) Bit_counter lt 0 else if
(inc_Bit_counter 1) Bit_counter lt Bit_counter
1 if (shift 1) RCV_shiftreg
lt Serial_in, RCV_shiftregword_size -
11 if (load 1) RCV_datareg
lt RCV_shiftreg end end endmodule
12
Simulation Results
13
Simulation Results
14
UART Transmitter
15
Data In Module
//XMT_DATA.V //input data register for
UART module XMT_DATA (data_in, clk, ldxmt,
XMTDATA) input 70 data_in input clk,
ldxmt output 70 XMTDATA reg 70
XMTDATA always _at_(negedge clk) if (ldxmt)
XMTDATA lt data_in endmodule
16
Transmitter Shift Register Module
//xmt_shift.v //shift register for serial
transmission module xmt_shift (data_in, clk, ld,
shift, clear, serial_out) input 70
data_in input clk, ld, shift, clear output
serial_out reg 90 XMT reg
serial_out always _at_(negedge clk or negedge
clear) if (!clear) begin XMT lt 10 'b
1111111111 serial_out lt XMT0 end els
e if (ld ) XMT lt 1'b1, data_in,
1'b0 else if (shift) XMT, serial_out
lt 1'b1, XMT else XMTltXMT endmodule
17
Bit Count Module
//BitCount.v //register to count bits as they are
transmitted module BitCount(clk, inc, clear,
eq9) input clk, inc, clear output eq9 reg
30 COUNT reg eq9 always _at_(posedge clk or
negedge clear) if (!clear) begin eq9 lt 0
COUNT lt 0end else if (inc) begin
if (COUNT lt 8) begin COUNT lt COUNT 1eq9
lt 0end else if (COUNT 8) begin
COUNT lt 0 eq9 lt 1end else if (COUNT gt 8)
begin COUNT lt 0 eq9 lt 0end
end endmodule
18
Controller Module
//cntl.v //controller for UART TRANSMITTER module
cntl (byte_ready, eq9, reset, T_byte, inc,start,
shift, clear, ldxmt, ldXMT_shift, clk) input
byte_ready, eq9, clk, reset, T_byte output inc,
start, shift, clear, ldxmt, ldXMT_shift reg
ld_xmt, start, shift, clear1, inc, ldxmt,
ldXMT_shift reg 10 state always _at_(posedge
clk or negedge reset) begin clear
1'b1 if (!reset) begin state lt
0 clear lt reset end
else case (state) 0 if
(byte_ready) begin ldxmt lt 1'b1 clear lt 1
state lt 1 end else state lt 0
1 begin ldXMT_shift lt 1'b1 ldxmt lt 1'b0
state lt2 end 2 begin
ldXMT_shift lt 1'b0 if (T_byte)

begin
start lt 1 state lt 3 end else state lt
2

end
3 if (!eq9) begin shift lt1 inc lt 1 start lt
0 state lt 3 end else begin inc lt 0
shift lt 0 clear lt 0 state lt 0 end
endcase end endmodule
19
Top Level Module
//uartxmt.v //toplevel file for uart xmtr module
uartxmt (datain, byte_ready, T_byte, clk, reset,
serial_out, ld, ldxmt, clear, data) input 70
datain input byte_ready, T_byte, clk,
reset output serial_out, ld, ldxmt,
clear output 70 data //for
instrumentation //instantiate
modules XMT_DATA xmtdatain (datain, clk, ldxmt,
data) xmt_shift xmtshift (data, clk, ld, shift,
clear, serial_out) BitCount count (clk, inc,
clear, eq9) cntl controller (byte_ready, eq9,
reset, T_byte, inc, start, shift, clear, ldxmt,
ld, clk) endmodule
20
Simulation
Controller Delay between Bits (Latency)
21
Example Problems

• Approximately three bit-time delay between end of
  stop bit and next start bit
• Part of problem due to mechanizing interface
  register with the transmission controller
  (introduces an extra clock)
• Other delays due to controller design and module
  design
• e.g. State machine mechanization is straight
  forward but not optimum
• Optimizing state machine can easily eliminate
  two-bit times of delay

22
Clock Generator

• Need a variable clock for the transmitter and
  receiver
• Consider developing a module that does the
  following
• INPUT
• system clock
• output frequency selection
• OUTPUT
• Transmitter
• Bit Rate Clock
• Receiver
• Bit Rate Clock
• Sampling Clock

23
Strategy
Table supports counts for ½ the period of the
respective clock.
Count 3 edges of system clock and transition
24
Partial Verilog
always _at_(posedge sys_clock) begin if
(s_count 0) begin sample_clock
!sample_clock s_count sample_count end else
s_count s_count -1 if (b_count 0) begin
bit_clock !bit_clock b_count bit_count
end else b_count b_count -1 end
25
Sample Timing
System Clock 5 MHz Bit Clock 115 Kbps
26
Serial Port Test Software

• Computers in 351G and 302 have a suite of test
  software which allow you to send characters to
  the serial port.
• WINCOMM is the most flexible since it allows
  selection of the bit rate from a drop down menu
  and allows character entry in a dialog box.
• Other programs provide fixed bit rate and run in
  a console window.
• Use this to send characters to your project boards

27
Hardware Issues

• You must construct a level shifter or obtain a
  level shifter for the FPGA reduce the RS-232
  12.5 V to 0 5 V. The device will be destroyed
  if this is not done. The boards you will use
  have a level shifter circuit connected to the
  DB-9 connector.
• Us the logic analyzers in 351 G to monitor your
  hardware. Bring out some of the internal signals
  for instrumentation purposes. (Beware of pin
  limitations)