Core Technology Demonstration on

1

• OptoElectronics Research Group

• Electrical Engineering Department, UCLA

• Core Technology Demonstration on
• Ultra Fast Wavelength Hopping OCDMA

• E. Chen, H. Chan, Y. Yang
• PI E. Yablonovitch
• Co-PI's R. Wessel, I. Verbauwhede, M.C. Wu, B.
  Jalali

2

• The Basic Idea

• What is OCDMA?

Wavelength-time Matrix
2 2 2 2 2 2 2 2 2 2
1
2
1
1 1 1 1 1 1 1 1 1 1 1 1
2
1
1
2
1
1
1
1
1
1
1
1
Wavelength
2
1
1
Wavelength
Wavelength
1
2
1
2
2
2
2
2
2
2
2
2
2
2
Time
Time
Time
TDM
WDM
OCDMA
Legend
? user1,
? user2
1
2

• Advantages of OCDMA
• High level of security
• High efficiency
• Simple implementation switching is performed
  electronically

3

• High Level of Security in the case with only one
  user

Simple Frequency Hopping
OCDMA
Wavelength
4

• Introduction to the Core Technology Demostration

• Specifications

• Goals

Demonstrate the wavelength time concept using
discrete off-the-shelf electronic components by
hopping the data from 4 users randomly in a 4x4
matrix at 2.5 Gbps

• Dimensionality of 2-D matrix code 4X4, that is,
  4 wavelengths,4 time slots
• Minimum size of buffer per user 4
• Switch fabric for 4 users
• 16X16 non-blocking switches

• Timing

The time period of bit-level scrambling will be
.
A very DEMANDING requirement!!!

• To Resolve
• Use 16 bits buffer instead of 4 bits
• Ts6.4ns of scrambling time

5

• Transmitter Side Schematic

155Mbps
16X16 Switch
2.5Gbps
Data 2.5Gbps
116
161
User 1
l1
Modulator
Data
16X16 Switch
116
161
User 2
l2
Modulator
Data
16X16 Switch
41
116
161
User 3
l3
Modulator
16X16 Switch
Data
116
161
User 4
l4
Modulator
116
161
de-Serializer
Serializer
6

• Receiver Side Schematic

Data
16X16 Switch
l1
116
161
Detector
User 1
Data
16X16 Switch
116
161
Detector
User 2
l2
Fiber
14
l3
Data
16X16 Switch
116
161
Detector
User 3
16X16 Switch
Data
l4
116
161
Detector
User 4
Hopping
pattern
116
161
de-Serializer
Serializer
7

• Switching Fabrics

Network implementing 16X16 Banyan network using
56 2X2 switches
8

• Switching Implementation

• Vitesse VSC830 2.5Gbps Dual 2x2 Crosspoint Switch

• Insight Virtex-II MB1000 FPGA Development Kit

• (Backup Approach)

• (Main Approach)

• Easier to meet critical timing requirements
• Easier integration between matrix and code
  generator
• Implementation flexibility and reprogrammability
• Easy-to-use modular development platform

• Up to 2.5GHz Clock, 2.5Gb/s NRZ Data Bandwidth
• Output Jitter lt40ps Peak-to-Peak
• Output Skew lt50ps
• Industry Standard 44 Pin PQFP Packaging
• Switch configuration time lt 1ns

9

• VSC830 Crosspoint Switch

• Select Function

10

• VSC830 Crosspoint Switch Testing Setup

Square Wave
DC -DC
To Oscilloscope
DC Signal
Square Wave
11

• Output Waveform after Switching

• Input Data DC CONSTANT SIGNAL
• Control Signals SQUARE WAVE
• Rise time 236.4ps and Fall time 214.8ps
• Duty Cycle about 50

12

• Synchronization Stragery

• Synchronize the Deserializer

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SYNC
Clock/O
SIG. GEN.
1 0 0 0 0
Clock
Vertical Data Alignment The bits from different
users at the same time period MUST go the same
outputs of corresponding deserializers.
116
Data
Data1/O
1000000000000000
SYNC
1 0 0 0 0
Data2/O
Clock
116
Data
1000000000000000
Data3/O
SYNC
1 0 0 0 0
Clock
Data4/O
116
Pulse the SYNC pin high for at least 4 clocks
period to shift the data alignment by dropping
one bit
Data
1000000000000000
SYNC
1 0 0 0 0
Clock
116
Data
1000000000000000
13

• Synchronization Stragery

• Synchronize the Serializer

Distribute the same reference clock from one of
the deserializers.
SYNC
Clock
Clock
161
116
Data
Data
Clock
Ref. Clock
SYNC
Clock
Clock
161
116
Data
Data
Clock
Ref. Clock
SYNC
Clock
Clock
161
116
Data
Data
Clock
Ref. Clock
SYNC
Clock
Clock
161
116
Data
Data
Clock
Ref. Clock
14

• PCB Integrated Optical Components

• 2.7Gbps DWDM Transmitter Module (57TM)
• 0.75dBm average optical power output
• 0.3-1.6VP-P input sensitivity data and clock
  voltage
• Made as a complement of 54RM Optical Receiver
  Module

• 2.7Gbps Optical Receiver Module (54RM)
• Integrated 3R Full Clock and Data Recovery
• Output Rise/Fall time about 150ps
• LVPECL output w/ Internal termination
• -30dBm sensitivity

15

• Summary

• Design a system that implement a secure method of
  data transmission through an optical fiber
• Encode each of the data bits in both time and
  frequency

Data 1
l1
Modulator
Space Division Switch small buffer
Data 2
l2
Fiber
Modulator
41
Transmitter
Data 3
l3
Modulator
Data 4
l4
Modulator
Data 1
l1
Detector
Space Division Switch small buffer
Data 2
l2
Detector
Receiver
14
Data 3
l3
Detector
Data 4
l4
Detector
Hopping
pattern