The AssociativeSkew Clock Routing Problem

1
The Associative-Skew Clock Routing Problem

• In memory of Mr. Patrick Catapano, Jr. of
  Motorola Corporation and his contributions to
  modern chip implementation methodology
• Yu Chen (UCLA)
• Andrew B. Kahng (UCLA)
• Gang Qu (UCLA)
• Alexander Zelikovsky (Georgia State)
• Supported in part by grants from Cadence Design
  Systems, Inc. and the MARCO (SRC/DARPA) Gigascale
  Silicon Research Center, and by a GSU research
  initiation grant.

2
Introduction

• Zero-Skew clock routing
• Associative-Skew Problem
• Example potential gain
• 3 composing methods
• optimal RSMT
• optimal joining
• optimal merging
• improves over GDME
• Testbed random sink sets
• Experiments
• Conclusion

3
Model

• Set of sinks S s1, , sn and source s0
• Sink delay t(s0, si)
• Skew between two sinks
• skew (si , sj) t(s0 , si )- t(s0
  , sj )
• Skew of a tree T maximum skew between sinks
• Objective minimize wirelength, such that skews
  between certain (all) pairs of sinks are small

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Relevant Clock Routing

• Zero skew over ALL sinks
• Zero-Skew Tree (ZST) literature
• Deferred-Merge Embedding (DME)
• optimal with the given topology
• Greedy-DME finds high-quality topology
• Almost zero skew over ALL sinks
• Bounded-Skew Tree (BST) literature
• solvable with DME-like approaches
• Zero skew over SUBSETS of sinks
• zero skew inside each subset
• no skew constraints between subsets

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Associative-Skew Problem

• Given Set of sinks S partitioned into disjoint
  subsets S S1? ? Sk
• Construct a Steiner tree connecting all sinks
  with a root S0 to achieve
• zero skew within each subset Si
• unconstrained skew between subsets
• Real-world bounded global skew
• skew in subsets lt 1 gate delay
• latch-to-latch 0-level datapaths
• 0-level paths quite small
• skew between subsets lt 12 gate delays

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Potential Wirelength Gain

• Potential gain is logarithmic
• each subset has single sink, Si 1 all
  sinks on a segment
• standard Steiner minimum tree may be log k times
  shorter than zero-skew tree

1
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Potential Wirelength Gain

• Potential gain is logarithmic
• each subset has single sink, Si 1 all
  sinks on a segment
• standard Steiner minimum tree may be log k times
  shorter than zero-skew tree

1
2/7
4/7
1/7
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Heuristic H0

• All our heuristics combine GDME solutions for
  each sink subset into single tree with common
  root
• H0 k-Greedy DME
• Greedy DME for each subset Si
• join the roots with any rectilinear Steiner
  minimum tree heuristic
• Can do better connect root of B to any point in A

H0
H1
A
A
B
B
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Heuristic H1

• H1 H0 but connect root from any internal point
• For each ordered pair of ZSTs A ZST(Si), B
  ZST(Sj),
• find optimal joining shortest edge from a
  point in A to root(B)
• Full directed graph G nodes ZST(Si), arcs
  optimal joinings
• Find optimal branching (directed MST) in G
• O(k2) - Tarjan (1977), Camerini-Fratta-Maffiol
  i (1979)

Directed graph G with optimal branching
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Better Merging

• Potential gain of total wirelength of B

A
A
B
B

• Given Given two ZSTs A and B and insertion
  delay offset w skew between sinks in A and B
  from root(A)
• Find min cost tree T(A,B,w)
• rooted at root(A)
• containing A
• offset w between path delays of sinks in A and
  sinks in B

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Optimal Slice Merging Algorithm

• For each v in B
• Find merge (v) merging cost of v to A with
  offset w
• Find adj(v) adjusted cost of root(B)-v-path
• gain(v) adj(v)-merge(v)
• Sum of gains over slice gain of slice
• Find optimal slice by preorder/postorder traversal

r(A)
A
u
merge(v) cost of thick edge adj(v) cost of
dashed edges divided by 2L, L edge level in
B slice roots of subtrees of B joined to points
of A
B
u
r(B)
v
s2
s
s1
T(A,B,w)
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Wirelength Gain over GDME
(-2,2)
(2,2)
(-2,2)
(2,2)
(1,1)
(-1,1)
(1,1)
(-1,1)
Root(0,0)
Root(0,0)
(1,-1)
(-1,-1)
(1,-1)
(-1,-1)
(-2,-2)
(2,-2)
(-2,-2)
(2,-2)
Optimal Slice Merging
Greedy DME with offset
Gain for this instance 28
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Testbed Random Sink Sets
Class 1 Shift
Class 2 Ring
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Experimental Results (Shift)
Experimental data for n-point sets randomly
generated in K shifted square regions Time1
refers to H2 runtimes Time2 refer to GDME
runtimes
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Experimental Results (Shift)
Runtime improvement since GDME is nonlinear
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Experimental Results (Shift)
H2 is losing to GDME with offsets
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Experimental Results (Ring)
Runtime improvement since GDME is nonlinear
18
Experimental Results (Ring)
Average wirelength improvement ? 7
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Conclusions Future Work

• We introduced the Associative-Skew Problem
• We suggested a series of heuristics
• outperform GDME for separated sink subsets
• GDME is good otherwise
• Open issues
• find a consistently better heuristic
• solve the ASP with limited-height (sub)trees