From Transistors To Computers

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From TransistorsTo Computers
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Gajski and Kuhns Y Chart
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Discovery of the Electron -- 1898
Cathode Tube
J. J. Thomson
Electric Field -- corpuscle
Cavendish Labs
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The Transistor
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The Vacuum Tube
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The FirstPoint-Contact Transistor1947
Bell Labs Museum
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Bell Labs
The FirstJunction Transistor1951
M1752 Outside the Lab
Lab model
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The Field Effect Transistor
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The Transistor
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Texas Instruments First IC -- 1958
Jack Kilby
Robert Noyce Fairchild Intel
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CMOS Circuits
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Implementing Gates
A
Relays
A
A
C
C
C
B
B
pMOS transistor A-B closed when C 0 (normally
closed)
nMOS transistor A-B closed when C 1 (normally
open)
B
Normally open Normally closed
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CMOS Circuits
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Logic Circuits
X
Y
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Logic Circuits
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(No Transcript)
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Logic Circuits - Functions
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Logic Circuits - Multiplexers
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4-line 2 x 1 Mux
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n-line 2 x 1 MultiplexerLab 1
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VHDL n-line 2 x 1 Multiplexer
library IEEE use IEEE.std_logic_1164.all   entit
y mux2g is generic(widthpositive) port
( a in STD_LOGIC_VECTOR(width-1 downto
0) b in STD_LOGIC_VECTOR(width-1 downto
0) sel in STD_LOGIC y out
STD_LOGIC_VECTOR(width-1 downto 0) ) end
mux2g   architecture mux2g_arch of mux2g
is begin mux2_1 process(a, b, sel) begin
if sel '0' then y lt a
else y lt b end if end
process mux2_1 end mux2g_arch
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ALU1- Shifting, Incr, and Decr Lab 2
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Logic Circuits - Binary Adder
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Logic Circuits - Binary Adder
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Logic Circuits - Full Adder
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Binary Adder/Subtractor
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ALU2 Arithmetic and Logic InstructionsLab 3
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ALU3 Comparators Lab 4
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CMOS Circuits
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Latches and Flip-Flops
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Latches and Flip-Flops
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Latches and Flip-Flops
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State Machines
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ALUs, Registers
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An n-bit Register
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A Function Unit (ALU1 ALU3)
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ALU
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Datapath
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Datapath
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A Single-Cycle Processor Lab 5
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Program Counter and Program ControlLab 6
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Processor
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Originally with Transistors
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A Close Up
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(No Transcript)
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W8ZProcessor
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The FC16 Forth Core
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Data Stack Lab 7
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Return StackLab 8
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The WC16 WHYP Core Lab 9
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Multi-cycle Computer
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Pipelined Computer
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CISC Processor
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QuantumComputer