An Experimental Study of Tester Yield and Defect Coverage

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An Experimental Study of Tester Yield and Defect
Coverage

• Jose T. de Sousa
• INESC/IST, Technical University of Lisbon
• 1000 Lisboa, Portugal
• jose.desousa_at_inesc.pt
• Vishwani D. Agrawal
• Circuit and Systems Research Lab
• Agere Systems, Murray Hill, NJ 07974 USA
• va_at_agere.com
• IEEE International Test Synthesis Workshop, Santa
  Barbara, CA

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VLSI Chip Yield

• A manufacturing defect is a finite chip area with
  electrically malfunctioning circuitry caused by
  errors in the fabrication process.
• A chip with no manufacturing defect is called a
  good chip.
• Fraction (or percentage) of good chips produced
  in a manufacturing process is called the yield.
  Yield is denoted by symbol Y.
• Cost of a chip

Cost of fabricating and testing a
wafer --------------------------------------------
------------------------ Yield x Number of chip
sites on the wafer
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Clustered VLSI Defects
Good chips
Faulty chips
Defects
Wafer
Clustered defects (VLSI) Wafer yield 17/22
0.77
Unclustered defects Wafer yield 12/22 0.55
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Yield Parameters

• Defect density (d ) Average number of defects
  per unit of chip area
• Chip area (A )
• Clustering parameter (a)
• Negative binomial distribution of defects,
  p (x ) Prob(number of defects on a chip x )

G (ax ) (Ad /a) x ------------- .
---------------------- x ! G (a) (1Ad /a)
ax
where G is the gamma function a 0, p (x ) is a
delta function (max. clustering) a , p (x )
is Poisson distr. (no clustering)

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Yield Equation
Y Prob( zero defect on a chip ) p (0)
Y ( 1 Ad / a ) - a

Example Ad 1.0, a 0.5, Y 0.58
, Y e -- Ad
Unclustered defects a

Example Ad 1.0, a , Y 0.37
too pessimistic !
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Defect Level or Reject Ratio

• Defect level (DL) is the ratio of faulty chips
  among the chips that pass tests.
• DL is measured as parts per million (ppm).
• DL is a measure of the effectiveness of tests.
• DL is a quantitative measure of the manufactured
  product quality. For commercial VLSI chips a DL
  greater than 500 ppm is considered unacceptable.

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Determination of DL

• From field return data Chips failing in the
  field are returned to the manufacturer. The
  number of returned chips normalized to one
  million chips shipped is the DL.
• From test data Fault coverage of tests and chip
  fallout rate are analyzed. A modified yield
  model is fitted to the fallout data to estimate
  the DL.

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Modified Yield Equation

• Three parameters
• Fault density, f average number of stuck-at
  faults per unit chip area
• Fault clustering parameter, b
• Stuck-at fault coverage, T
• The modified yield equation

Y (T ) (1 TAf / b) - b
Assuming that tests with 100 fault coverage (T
1.0) remove all faulty chips,
Y Y (1) (1 Af / b) - b
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Defect Level
Y (T ) - Y (1) DL (T )
-------------------- Y (T
) ( b TAf ) b
1 - -------------------- (
b Af ) b
Where T is the fault coverage of tests, Af is
the average number of faults on the chip of area
A, b is the fault clustering parameter. Af and
b are determined by test data analysis.

b
, Y (T ) e--TAf and DL(T) 1 -- Y (1)1--T
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Example SEMATECH Chip

• Bus interface controller ASIC fabricated and
  tested at IBM, Burlington, Vermont
• 116,000 equivalent (2-input NAND) gates
• 304-pin package, 249 I/O
• Clock 40MHz, some parts 50MHz
• 0.45m CMOS, 3.3V, 9.4mm x 8.8mm area
• Full scan, 99.79 fault coverage
• Advantest 3381 ATE, 18,466 chips tested at 2.5MHz
  test clock
• Data obtained courtesy of Phil Nigh (IBM)

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Test Coverage from Fault Simulator
Stuck-at fault coverage
Vector number
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Measured Chip Fallout
Measured chip fallout
Vector number
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Model Fitting
Unclustered faults Af 0.31
Y (1) 0.7348
Clustered faults Af 2.1 and b 0.083
Chip fallout and computed 1-Y (T )
Y (1) 0.7623
Measured chip fallout
Stuck-at fault coverage, T
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Computed Defect Level
Unclustered faults
Defect level (ppm)
Clustered faults b 0.083
Stuck-at fault coverage ()
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Reexamine Assumption

• Assumption 100 fault coverage leads to zero
  defect level.
• Reality 100 defect coverage leads to zero
  defect level.
• Must examine the two coverages.

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Fault vs. Defect Coverage
Fault coverage Defect coverage

• Coverage of stuck-at faults detected by
  vectors.
• Faults are countable.
• Alternative definition f(T) Prob(detection by
  T vectors a fault is present)
• All faults assumed equally probable on a faulty
  chip.
• Determined theoretically.

• Coverage of real defects detected by vectors.
• Many types, large numbers.
• Alternative definition d(T) Prob(detection
  by T vectors a defect is present)
• Each defect may have a different probability of
  occurrence.
• Determined experimentally.

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Defect Coverage
d (T ) Prob (detection by T vectorschip
defective) Prob (failure by T
vectors) -------------------------------
------------ 1 Y (1)
1 Y (T ) --------------
1 Y (1) Measured yield, Y (T ), and
estimated true yield, Y (1), can provide a
statistical estimate for defect coverage.
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Defect and Fault Coverages
Defect coverage d
Fault coverage f
Coverage
Vector number
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Defect vs. Fault Coverage
Defect coverage, d
d gt f
dlt f
Fault coverage, f
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Conclusion

• Defect coverage can be determined from the
  measured test data.
• Assumption Test must be capable of activating
  the defect, e.g., only data from at-speed test
  can determine the coverage of delay defects.
• The assumption, DL 0 at f 100, may be
  justified since fault coverage appears to be more
  pessimistic than defect coverage.
• Any coverage is a transformation of test data
• Vector 0 coverage 0
• Vector infinity coverage 1
• Unclustered fault assumption adds pessimism.

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