UPRMHPA Seminar Richard Antley TIFellow Mike Yazdani PE Manager - PowerPoint PPT Presentation

Title: UPRMHPA Seminar Richard Antley TIFellow Mike Yazdani PE Manager


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UPRM-HPA SeminarRichard Antley TI-FellowMike
Yazdani PE Manager

• 1st session
• HPA Product Engineering
• January 26th, 2008

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Profile Mike Yazdani

• BSEE 1983 UTA
• MSEE 1990 SMU
• MSEM 2001 SMU
• Hired into TI as Product Engineer 1986
• Worked as Product, Test, Design engineer
• Worked on Standard Logic, ADCs, DACs, CODECs, and
  Audio products.
• Now Product Engineering Manager in charge of
  sustaining Audio and Imaging Products at TI

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Agenda

• Presented by Mike Yazdani
• SC business overview
• New Product Development
• PE/TE roles
• Why test
• How to test
• Limit setting GRR - Temp and Machine
  (Capability) GBs
• QA testing
• Production testing
• Product sustaining
• Characterization of a product
• Wafer fab and probe test concepts.
• Quality and reliability

• Presented by Richard Antley
• Data sheet understanding
• A simple OP-Amp Analog
• A simple ADC/DAC CODEC
• ATE Tester Overview
• Tools, Testers
• What is precision
• What is accuracy

This is a Product and Test Engineering seminar
designed to increase the understanding of
senior and graduate level students of PE/TE.
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Engineering roles at TI

• Product Engineer
• Test Engineer
• Design engineer
• FAB MQ engineer
• Systems engineer
• Marketing engineer
• Planning
• Finance
• Process engineer
• FAB Yield engineer
• FAB Product engineer

• Packaging engineer
• Project Manager
• Facilities engineer
• Technical Staff
• Equipment engineer
• EDA
• PCB
• A/T product engineer
• Software engineer
• Define, Design, Validate
• Application engineer
• Technical writer

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SC business overview

• SC group in TI is organized in 5 SBEs
• Strategic Business Units
• HPA, HVAL, WTBU, ASP, DLP
• 14 billion in 2007, 25.3 PFO

• 15,900 in The Americas 12,600 in Texas
  11,300 in North Texas 10,400 in Dallas Area
• 8,800 in Asia
• 2,400 in Japan
• 3,200 in Europe

Approximately 30,300 employees worldwide
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TI has over 75 Years of Innovation

• TI engineer Jack Kilby invented the worlds first
  integrated circuit in 1956, an invention that
  changed the world forever and garnered him a
  Nobel Prize in 2000
• TI invented the first calculator in 1967 weighing
  4 ½ pounds and costing 2500. Today, TI has
  shipped more than 20 million graphing
  calculators.
• TI has won two Emmy Awards for its DLP
  technology
• More than half of the worlds cell phones use TI
  technology
• 75 of the worlds PCs use TI for power
  management and data storage
• TI DSPs are so fast they are listed in the
  Guinness Book of World Records
• TI builds some of the worlds most advanced
  seminconductor designs on 300 mm silicon wafers
  with leading-edge 65-nanometer process
  technology

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TI Businesses
Semiconductor 11.8 B
Education Technology .5B
Semiconductors
2005 TI Revenue By Segment (B) 12.3B
Continuing operations, excludes the divested
Sensors Controls business.
Education Technology
B
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Segway Human Transporter
Digital Motor Control
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HPA New Product Development
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HPA New Product Development

• New product Development is divided into several
  sections
• Kickoff phase This is where the project is
  evaluated from a financial, market, schedule
  fusibility
• Validation phase In this phase a schedule is in
  place that had valid dates up to and including
  the Release To Market. Marketing numbers are
  reviewed again.
• Create phase This is where the device is
  designed, and fabricated. Meanwhile test hardware
  and software is prepared.
• Evaluate phase This is where the device is
  evaluated vs. specified parameters both on the
  ATE and on Bench. Product also goes through
  varous qualification testing
• RTM phase This is where all hardware, software,
  qualification, and other required material (Data
  sheet, pricing, COB, BOM,) are set and device is
  ready for mass production.
• Ramp To Volume phase In this phase, we ensure
  all yields and test times and optimized.
  Multisite testing is added for devices that have
  high volumes.

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PE/TE roles

• Test Engineer
• Reviews and understands the data sheet of a given
  product. All specs as well as theory of
  operations are clearly defined and understood
• Understands how to define and test all specified
  parameters. Can identify bench instruments needed
  to test the parameters.
• Understands at least one Automatic Test Equipment
  and its set of instruments and capabilities
• Can write software to operate the ATE to test a
  given product.
• Design hardware to test device. HIB, PIB
• Familiar with schematic capture tools as well as
  layout of PCB

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The Complete Signal Processing Chain and Power
Architecture
Analog Signal Conversion to Digital
The Real World
Signal Conditioning
Temperature Pressure Position Speed Flow Humidity
Sound Light
Power Management
Digital Signal Processor
Digital Signal Conversion to Analog
Interface
Signal Conditioning
Clocks timers
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PE/TE roles

• Product Engineer
• Understand the entire flow of the semiconductor
  development process as well as sustaining devices
  in production.
• Understands fabrication flows and factory process
  flows.
• In most cases serves as project manager for NPD
  phase.
• Understands and performs product qualification.
• Can help is identifying qual and test failures.
• A very good understanding of statistics
• Monitors and maintains devices in production both
  probe and final test.
• Yield monitor, analysis,
• Low yield disposition
• New package spins
• 70-30.

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Why Test

• All devices that leave our factory must meet all
  specified parameters at all specified conditions.
• Because of this we must fully test or SBD for all
  specified parameters.

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How to test

• Bench characterization
• Functional
• Parametric
• ATE. Full 100 test across all specified temps
  or guard bands in place to meet temp specs.
• Use various ATEs. HP, Teradyne, LTX, ETS,..
• Use handlers. Delta, Multitest, YoKowa,
• Use high performance sockets.

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VLCT
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VX3 Fusion
Integra Flex
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200mm TSK Prober
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Delta Castle
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Delta Flex Pick and place
Multi test - Gravity
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Multitest
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• Continuity
• Purpose of Continuity Testing
• ATE to Test Head connection

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• Purpose of Continuity Testing
• Verify Bond Wire Connection between die bond pad
  and package lead frame

10pin
No bond wire!
3pin
1pin
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• Continuity
• Continuity Test Technique
• On chip protection diodes
• Protect input and output from Electrostatic
  Discharge (ESD) and other overvoltage
• Pins have either one or two reverse biased diodes

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Limit setting GRR - Temp and Machine
(Capability) GBs

• Limits are set to prevents bad units being
  shipped to customers.
• Guard bands are calculated based on the GRR which
  is a Temp drift study and test setup capability.
• Temp across specified temp.
• I -40 to 85C. Room is 25C
• C 0 to 70C.
• Test setup
• HIB, tester, Sites on the HIB

This is the GB for Temp variation if only room
temp testing is done.
This is the GB for Capability of the test
solution.
Gt G1G2 2 Gt less than 10 of spec
USL
FTL
LSL
FTL
G1
G2
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QA LAT testing

• All production lots will be sample tested for lot
  acceptance testing
• A sample of 200 or 315 (depending on the lot
  size) is pulled and retested to the data sheet
  limits.
• Yield should be 100 or the entire lot will have
  to be retested.
• This depending on the sample size will ensure a
  ceratin AQL or DPPM.
• This will catch binning, handling, jam count,
  issues
• TestSPC in HPA will replace LAT

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Production testing

• Refer to the pictures in the how to test
  section of this presentation and the day 2 of the
  August presentation.
• Reminder All devices shipped from TI to our
  customers are 100 tested at least once to the
  specified parameters.

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Characterization of a product

• Usually done on the bench
• One a few devices
• Used lab instruments, PC, software,.
• Verifies most all parameters/function
• Also can be done on ATE for corr.

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Wafer fab and probe test

• Wafer fabrication site are where we process Raw
  wafers to a final device.
• Some 9 to 38 masks are used to make devices.
• Make CMOS, BiPolar, BiCMOS processes
• TI has 10 wafer fabs and 8 assembly test
  facilities that turn raw silicon wafers into
  quality packaged chips that are vital for end
  products like cell phones, PDAs, MP3 players,
  and digital cameras.
• Probe testing is done at the end of fab
  processing to identify and remove bad dies from
  assembly and test.
• A wafer map (see picture) is created after probe
  testing.

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200mm TSK Prober
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VLCT docked to TSK prober
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Wafer Ring
Chuck
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Probe Card
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Probe Card
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Probe Marks
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Quality and Reliability

• All new devices, new packages, new fab process
  and any change to an existing device is
  production will have to be qualified according to
  TIs internal specs.
• Tests included for qualification are
• SSLT or BI, or HTOL (dynamic and Static)
• HAST
• Temp Cycle or Thermal shock
• ESD
• Latch up
• Characterization
• Autoclave

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Packaging
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Semiconductor Packaging
The semiconductor package provides the electrical
interconnect between the integrated circuit and
the printed circuit board.
Epoxy encapsulant
Leads
Circuit board traces
Bond wires
Integrated circuit
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TI Offers A Wide Package Portfolio, Including
Quad Flatpack No Leads (QFN)
Thin Quad Flatpack (TQFP)
Small Outline No Leads (SON)
Small Outline Transistor Package (SOT23)
Transistor Outline (TO236)
Mini Small Outline Package (MSOP)
Shrink Small Outline Package (SSOP)
Heat Sink Thin Quad Flatpack (HTQFP)
Surface Mount Header (DDPak)
Small Outline Integrated Circuit (SOIC)
Thin Shrink Small Outline Package (TSSOP)
Small Outline Transistor (SOT223)
Plastic Dual-In-Line Package (PDIP)
Power Modules
Heat Slug Small Outline Integrated Circuit
PowerPad Small Outline Package (HSOP)
Transistor Outline (TO220)
Power Small Outline Package (PSOP3)
Analog Mirror Packages
Thermally Enhanced BGAs
MicroStar JR Chip Scale Pkg (uJR
BGA) MicroStar Ultra Thin Land Grid Array Chip
Scale Package (uUT LGA)
MicroStar BGA Chip Scale Tape
BGA (uBGA) Laminate Chip Scale BGA (nFBGA)
Wafer Scale Package (WSP)
Flip-Chip Power Packages
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Assembly process
DIE ATTACH/CURE
SAW
WIRE BOND
IR REFLOW
BALL ATTACH
MOLD
FLUX WASH
VM V/M Lot Accept
BALL INSPECT
PACKPACK LOT Accept
inc. Bake
SHIP

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Purpose of the Semiconductor Package

• Provide the electrical connection between the
  semiconductor and end application.
• Semiconductor I/O are at very fine pitch (0.060mm
  is not unusual)
• End product I/O are often 0.5 to 0.8mm pitch.
• The semiconductor package provides environmental
  protection against
• Heat
• Corrosion
• Mechanical damage.

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• Thank you