MINFLOTRANSIT: MinCost Flow Based Transistor Sizing Tool - PowerPoint PPT Presentation
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MINFLOTRANSIT: MinCost Flow Based Transistor Sizing Tool
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Dept. of Electrical and Computer Engineering. University of Minnesota, ... Minimize Area [Sum of Transistor Widths] subject to. Delays specifications on IO paths ... – PowerPoint PPT presentation
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Title: MINFLOTRANSIT: MinCost Flow Based Transistor Sizing Tool
1
MINFLOTRANSIT Min-Cost Flow Based Transistor
Sizing Tool
- Vijay Sundararajan
- DSP RD Center Texas Instruments, Dallas
- Sachin S. Sapatnekar
- Keshab K. Parhi
- Dept. of Electrical and Computer Engineering
- University of Minnesota, Minneapolis
2
Introduction
- Objective
- Minimum circuit area for target speed
- Previous Work
- Optimal techniques (slow)
- Suboptimal techniques (potentially inaccurate)
- Chen et al., ICCAD98 fast technique based on
Lagrangian relaxation, demonstrably fast on adders
3
Introduction (Contd.)
- Notable approaches
- Static TILOS, posynomial based exact approaches
- Dynamic JiffyTune IBM
- Summary of previous exact approaches
- Based on posynomial delay models
- Resort to convex programming
- Polynomial time, yet slow for large instances
- Fast approach Chen et al. ICCAD98 - restricted
delay model - Our proposed solution
- Exact extremely fast on various benchmark ckts
- Applicable to a possibly larger class of delay
models
4
Common Delay Model
Definitions
- Posynomial
- Elmore Delay
5
Problem Formulation
- Minimize Area Sum of Transistor Widths subject
to - Delays specifications on IO paths
- Minimum and maximum limits on transistor widths
6
Proposed Solution
Proposed Method
- Two-phase iterative relaxation
- ? D-phase Delay budgeting (find Ds)
- ? W-phase Constant delay sizing (find Ws)
7
Area-Delay Relationship
- For each gate delay(i).xi - ?j aij . xj bi
- For the entire circuit (D - A) X B
- (D - A) is upper triangular, therefore easily
invertible - Example (D-A) matrix
8
Area-Delay Relationship (Contd.)
- Assume small perturbations
- Change in area is a negative linear
- combination of change in delays
9
D-Phase Delay Budgets
- Sundararajan and Parhi, DAC 99
10
D-Phase Delay Re-budgeting
Fictitious Specific Delay Unit (FSDU)
3/0/3
PI
1/0/1
1
7/0/7
2
5/0/5
2
2
2/1/3
PI
1
3
0/1/1
2
2
3
1
2
2
2/2/4
1
1
PI
1/1/2
3
1
1
4/2/6
7/1/8
11
FSDU-Displacement
Formalizing FSDU-Displacement
- Associate an integer valued label r(v) with each
vertex v - FSDUs after FSDU-Displacement r(v) - r(u) d
12
FSDU-Displacement
Problem Modeling
V
V
d
d
U
D
U
W
e
W
e
- Insert a Dummy node between a vertex and its
fanouts - The minimum number of FSDUs at the output of U
can be shown to be given by r(D) - r(U)
13
D-Phase Optimization
Dual min-cost network flow
- D-phase
- Objective
- Constraints
14
Some Useful Math
Definitions
- Simple Discrete Monotonic Constraint
- where g, f are monotonic increasing functions
of their arguments - Simple Discrete Monotonic Program (SDMP)
- subject to SDM constraints
15
More About SDMP
Properties
- SDMP (Simple Discrete Monotonic Program)
- Has bounded variables
- Can be solved with a relaxation procedure
- Has a worst case complexity, O(VariablesConst
raints) - Problem formulation Similar to shortest path for
DAGs - Therefore solution Similar to Bellman-Ford
16
W-Phase is SDMP!
Constant Delay Budgets
- W-Phase
subject to
17
Putting It All Together
- MINFLOTRANSIT
- Size using TILOS
- Iterate D-phase and W-phase until convergence
- W-Phase SDMP
- D-Phase Min-Cost Network Flow
18
Comparison with TILOS?
- Example
- (both outputs equally critical)
- TILOS sizes the most sensitive gate at each
iteration - If A has a lower sensitivity than B, C ?
TILOS will size B, C in alternate passes - However, sizing A reduces the delay to both
outputs! - MINFLOTRANSIT uses a global view of the circuit
and may size gate A to meet timing requirements,
even if it is not the most sensitive
B
A
C
19
Experimental Results
- ISCAS85 Benchmark Ckts
- Delay spec 0.4 x delay of minimum-sized circuit
- Area Savings over TILOS
20
Experimental Results
- CPU Times of TILOS vs. MINFLOTRANSIT
21
Conclusion
- New approach to transistor/gate sizing
- Two-phase iterative relaxation
- D-phase
- W-phase
- Practically, the complexities are seen to be much
less - Provably convergent
- Efficient
- Up to 17 reduction in area over TILOS
- Only 3-4 times slower than TILOS
- Applicable to a more general class of models than
Elmore delays
22
Applicable Delay Models
- A delay model admits a simple monotonic
decomposition if delay is expressible as - (P, Q are monotonic increasing functions of their
arguments) - MINFLOTRANSIT is fast if
- (D-A) can be expressed as block-triangular
almost always
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