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PRARDIVA MANGILIPALLY

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Clock gating is one of the power saving techniques in which additional logic is ... Tools used: Modelsim, leonardo, Design Architect, Eldo. Technology: tsmc018 ... – PowerPoint PPT presentation

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Title: PRARDIVA MANGILIPALLY

1
32 BIT PARALLEL LOAD REGISTER WITH CLOCK
GATING

PRARDIVA MANGILIPALLY
ELEC 6270

2
OUTLINE

Objective
Basic idea
Basic gating circuit
Modified clock gating circuit
Design platform
Results
Conclusion

3
OBJECTIVE

To measure the average power for a 32 bit
parallel load register with and without clock
gating.
To compare the results for the same.
To study the effect of clock gating on power
consumption for a 32 bit parallel load register.

4
CLOCK GATING

Clock gating is one of the power saving
techniques in which additional logic is added to
a circuit to prune the clock tree ,thus disabling
portions of circuitry so that flipflops do not
change state.As a result switching power goes to
zero.

5
MODIFIED CLOCK GATING CIRCUIT
6
Design platform

Latchfree clock gating circuit
Tools used Modelsim, leonardo, Design Architect,
Eldo
Technology tsmc018
Clock frequency 50MHz
Operating voltage 1.8V

7
Pattern0000000

Without clock gating
Average power 242.6818U W

With clock gating
Average power 42.8374U W

8
Pattern111111111

Without clock gating
Average power 244.0567UW

With clock gating
Average power 27.4138UW

9
Pattern101010

Without clockgating
Average power457.2622uW

With clock gating
Average power 628.8430U W

10
PATTERN10111011

WITHOUT CLOCKGATING
AVERAGE POWER357.8213UW

WITH CLOCK GATING
AVERAGE POWER337.1065UW

11
PATTERN01000100

WITHOUT CLOCKGATING
AVERAGE POWER355.11064UW

WITH CLOCKGATING
AVERAGE POWER331.2031UW

12
PATTERN11011101

WITHOUT CLOCKGATING
AVERAGE POWER352.7703UW

WITH CLOCKGATING
AVERAGE POWER324.1347UW

13
PATTERN00100010

WITHOUT CLOCKGATING
AVERAGE POWER344.7696UW

WITH CLOCKGATING
AVERAGE POWER337.4078UW

14
INPUT12000000101000000101010000000000000000000000
00000000

WITHOUT CLOCK GATING
AVERAGE POWER288.4402UW

WITH CLOCK GATING
AVERAGE POWER165.1852UW

15
INPUT12 11111111101010111111010111111111111111111
111111111

WITHOUT CLOCKGATING
AVERAGE POWER289.1212UW

WITH CLOCKGATING
AVERAGE POWER146.8568UW

16
Power Reductions
Without clock gating With clock gating
TRANSITION DENSITY EXPECTED POWER (UW) OBSERVED POWER (UW) EXPECTED POWER (UW) OBSERVED POWER (UW) POWER REDUCTION ()
0.0000 244.0512 244.0567 68.7008 27.4138 88.77
0.0004 242.6944 242.6818 70.1134 42.8374 82.35
0.1000 262.4961 289.1212 182.0272 146.8568 49.21
0.1024 289.1168 288.4402 170.3126 165.1852 42.73
0.2500 357.7568 357.8213 340.1931 337.1065 5.51
0.5000 457.1456 457.2622 655.6832 628.840 -37.5
17
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18
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19
CONCLUSIONS

Clock gating technique effectively reduces
dynamic power in most of the cases.
However,it increases power when there are
transitions in every clock cycle.This increase is
due to the extra power consumed by the ex-nor and
nor gates in the clock gating circuit which
account to about 58 increase in total hardware.
If this increase in hardware could be reduced
then the power savings can be increased even in
the worst case which calls for the implementation
of a different clock gating circuit or the usage
of low power ex-ors discussed in the class.

20
REFERENCES

Class lecture slides at http//www.eng.auburn.edu
/vagrawal/ COURSE/ E6270_Spr09/course.html
Frank Emnett and Mark Biegel, Power Reduction
Through RTL Clock Gating, SNUG2000(This paper
discusses a method to avoid premature truncation
of the clock).

21
THANK YOU

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