ChannelandCircuitsAware, EnergyEfficient Coding for HighSpeed Links

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ChannelandCircuitsAware, EnergyEfficient Coding for HighSpeed Links

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Analysis of FEC and Trellis codes (implementation cost vs. BER) Experimental setup ... Theoretical analysis of Trellis and FEC codes ... – PowerPoint PPT presentation

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Title: ChannelandCircuitsAware, EnergyEfficient Coding for HighSpeed Links

1
Channel-and-Circuits-Aware, Energy-Efficient
Coding (for High-Speed Links)

Vladimir Stojanovic and Lizhong Zheng
Massachusetts Institute of Technology

2
Driver 1 Electrical I/O Challenges

40Tb/s I/O
With 10Gb/s per link
4000 transceivers
8000 high-speed I/O pairs
4000 mm2 in 0.13 µm technology
Power 1.6kW
40mW/Gb/s

3
Driver 1 8000 diff pairs - Density issues

Connectors
50 diff pairs/inch
160 long connector
Trace routing
50mils pitch
100 wide 4-signal layer line-card
Backplane less critical
Package
Package/Chip ball pitch (1mm / 200um)
1600 mm2 / 64mm2

4
Driver 1 Needs

Power
Reduce energy/bit to 2mW/Gb/s
Density
Increase data rate per link by 10x

5
How efficient are high-speed links?
Component cost
Scaling with data rate

2-3 orders more energy-efficient
Than traditional wireline systems
But, starting to pay the price for band-limited
channels

6
Link channels and data rates

Capacity very high 80-100 Gb/s
Even in legacy backplanes
Uncoded multi-tone data rates 40-50Gb/s
Very low BER requirements (10-15)
Peak transmitter power constraint

7
Opportunity for coding

Break the coding/equalization/modulation
hierarchy
Goal to minimize overall energy cost per bit
Coding is more energy-efficient in achieving the
low BER than modulation/equalization
Especially with lots of crosstalk and numerous
small reflections
Need new paradigms in code development to
specification
Non-Gaussian (system) noise
Circuit non-idealities
Crosstalk and residual channel memory (ISI)

8
Project plan

Phase 1 Link Simulation
Stochastic Link BER estimation with coding,
channel and noise memory
Phase 2 Power-Performance analysis
Analysis of FEC and Trellis codes (implementation
cost vs. BER)
Experimental setup
Phase 3 Design of new, energy-efficient codes
Propagate channel and circuit non-idealities to
the code design level
Phase 4 Implementation of new codes
Algorithms for efficient VLSI implementation of
new codes
Experimental verification

9
Phase 1 Link Simulation (under way)

Coded data, ISI, crosstalk and jitter all have
long memory
Huge state-space for Monte-Carlo simulation
Nearly impossible to simulate for BER targets of
10-15
Use Importance Sampling methods to get faster
simulations
Change the input distributions to enhance more
error events
Compensate in the end for the distorted input
distributions
Need to be careful in picking the input
distributions
Conditioning and Large Deviation Theory can help
with that

10
Phase 2 Performance characterization (under way)

Experimental setup
Xilinx fabric
Coder/Encoder
3-10Gb/s Rocket I/O links
Backplanes and line-cards (Rambus gift)
20 traces, HSD connectors
Roger, FR4, Nelco4000 dielectric
Counter-bored vs. not
Theoretical analysis of Trellis and FEC codes
Correlation of the link simulator to the
experiment

11
Simple example

Error detection
Simpler, potentially more energy-efficient than
error correction
CRC, extended Golay, Hamming and BCH codes very
efficient in error detection
Coder/decoders embedded easily in the serializer
and deserializer shift registers
BER targets VERY low (10-15)
Reasonably reliable back-channels already in use
BERlt10-6 (for adaptation and link configuration)
Use error detection and retransmission (ARQ)
Raw channel BER 10-6, packet length 20
Max 3 retransmissions per error to match overall
BER target of 10-15
BW overhead due to retransmission 0.002