VLSI Design

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VLSI Design

• Mao-Hsu Yen
• yenmh_at_mail.ntou.edu.tw

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Text

• John P. Uyemura Introduction to VLSI Circuits
  and Systems.
• ????
• ??20858917
• Tel [phone] ???
• Fax [phone]

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Chapter 1 Overview of VLSI 1.1 Complexity and
Design 1.2 Basic Concepts 1.3 Plan of the
Book 1.4 References
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Chapter 2 Logic Design with MOSFETs 2.1 Ideal
Switches and Boolean Operations 2.2 MOSFETs as
Switches 2.3 Basic Logic Gates in CMOS 2.4
Complex Logic Gates in CMOS 2.5 Transmission
Gate Circuits 2.6 Clocking and Dataflow Control
2.7 References
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Chapter 3 Physical Structure of CMOS
Integrated Circuits 3.1 Integrated Circuit
Layers 3.2 MOSFETs 3.3 CMOS Layers 3.4
Designing FET Layers 3.5 References
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Chapter 4 Fabrication of CMOS Integrated
Circuits 4.1 Overview of Silicon Processing 4.2
Material Growth and Deposition 4.3
Lithography 4.4 The CMOS Process Flow 4.5
Design Rules 4.6 References
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Chapter 5 Elements of Physical Design 5.1 Basic
Concepts 5.2 Layout of Basic Structures 5.3
Cell Concepts 5.4 FET Sizing and the Unit
Transistor 5.5 Physical Design of Logic
Gates 5.6 Design Hierarchies 5.7 References
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Chapter 6 Electrical Characteristics of
MOSFETs 6.1 MOS Physics 6.2 nFETCurrent-Voltage
Equations 6.3 The RC Model 6.4 pFET
Characteristics 6.5 Modeling of Small
MOSFETs 6.6 References
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Chapter 7 Electronic Analysis of CMOS Logic
Gates 7.1 DC Characteristics of the CMOS
Inverter 7.2 Inverter Switching
Characteristics 7.3 Power Dissipation 7.4 DC
Characteristics NAND and NOR Gates 7.5 NAND and
NOR Transient Response 7.6 Analysis of Complex
Logic Gates 7.7 Gate Design for Transient
Performance 7.8 Transmission Gates and Pass
Transistors 7.9 Comments on SPICE
Simulations 7.10 References
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Chapter 8 Design High-Speed CMOS Logic
Networks 8.1 Gates Delays 8.2 Driving Large
Capacitive Loads 8.3 Logical Effort 8.4 BiCMOS
Drivers 8.5 References
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Chapter 9 Advanced Techniques in CMOS Logic
Circuits 9.1 Mirror Circuits 9.2
Pseudo-nMOS 9.3 Tri-State Circuits 9.4 Clocked
CMOS 9.5 Dynamic CMOS Logic Circuits 9.6
Dual-Rail Logic Networks 9.7 References
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Chapter 10 System Specifications Using Verilog
HDL 10.1 Basic Concepts 10.2 Structural
Gate-Level Modeling 10.3 Switch-Level
Modeling 10.4 Design Hierarchies 10.5
Behavioral and RTL Modeling 10.6 References
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Chapter 11 General VLSI System Components 11.1
Multiplexors 11.2 Binary Decoders 11.3 Equality
Detectors and Comparators 11.4 Priority
Encoder 11.5 Shift and Rotation Operations 11.6
Latches 11.7 D Flip-Flop 11.8 Registers 11.9
The Role of Synthesis 11.10 References
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Chapter 12 Arithmetic Circuits in CMOS VLSI 12.1
Bit Adder Circuits 12.2 Ripple-Carry
Adders 12.3 Carry Look-Ahead Adders 12.4 Other
High-Speed Adders 12.5 Multipliers 12.6
Summary 12.7 References
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Chapter 13 Memories and Programmable Logic 13.1
The State RAM 13.2 SRAM Arrays 13.3 Dynamic
RAMs 13.4 ROM Arrays 13.5 Logic Arrays 13.6
References
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Chapter 14 System-Level Physical Design 14.1
Large-Scale Physical Design 14.2 Interconnect
Delay Modeling 14.3 Crosstalk 14.4 Interconnect
Scaling 14.5 Floorplanning and Routing 14.6
Input and Output Circuits 14.7 Power
Distribution and Comsumption 14.8 Low-Power
Design Considerations 14.9 References
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Chapter 15 VLSI Clocking and System Design 15.1
Clocked Flip-Flops 15.2 CMOS Clocking
Styles 15.3 Pipelined Systems 15.4 Clock
Generation and Distribution 15.5 System Design
Considerations 15.6 References
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Qualification Middle Term 30 Finals
30 Others 40
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Final Report Schematic Simulation Layout