TDT4160 Datamaskiner grunnkurs

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TDT4160 Datamaskiner grunnkurs

• Uke 3, time 1
• Haakon Dybdahl

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I dag

• Kort repload-store maskin
• Mikroarkitektur Kap 7
• Utføring av en instruksjon
• Fastkablet (eng hardwired)

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Load Store maskin
4
Load-Store maskin

• 32 registre, register 0 har alltid verdi 0
• Register 1 er reservert
• Register 31 brukes som stakkpeker
• Data blir plassert fra begynnelsen av minnet,
  adresse 0 (dette er definitivt en leke-maskin

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Litt enkel assembler

• data svar plass til resultat
• main
• load 2,12 12 inn i register 2
• load 3,24 24 inn i register 3
• add 4,2,3 adder registre, svar i R4
• store 4,svar overfør svar til svar
• stop
• end main

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Adressering i Load/Store Dark

• Litt spesielt i denne maskinen....
• Variabler starter på adresse 0...
• data 23 element1 (Havner i adresse 0)
• data 56 element2 (Havner i adresse 1)
• data svar (Havner i adresse 2)
• load 2,0,0 (henter verdi i adr. 0)
• load 3,0,1 (henter verdi i adr. 1)
• add 4,2,3
• store svar,0,2 (lagrer i adresse 2)

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Høynivå program
Kompilator
Assemblerkode Maskinkode
Assembler
8
Memory
MDR
MAR
Control
R
PC
0
R
Processor
1
IR
ALU
R
n
1
-
n
general purpose
registers
Figure 1.2. Connections between the processor
and the memory.
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Internal processor
bus
Control signals
PC
Instruction
Address
decoder and
lines
MAR
control logic
Memory
bus
MDR
Data
IR
lines
Y
R0
Constant 4
Select
MUX
Add
A
B
Sub
R
n
1
-
(
)
ALU
control
ALU
lines
Carry-in
XOR
TEMP
Z
Figure 7.1. Single-bus organization of the
datapath inside a processor.
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Figure 7.3. Input and output gating for one
register bit.
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Figure 7.4. Connection and control signals for
register MDR.
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Step
Action
1
PC
,
RB,
MAR
,
Read,
IncPC
out
in
2
WMF
C
3
MDR
,
RB,
IR
in
outB
4
R4
,
R5
,
SelectA,
Add,
R6
,
End
outA
outB
in
Figure 7.9. Control sequence for the instruction.
Add R4,R5,R6, for the three-bus organization in
Figure 7.8.
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Step
Action
1
PC
,
MAR
,
Read,
Select4,
Add,
Z
out
in
in
2
Z
,
PC
,
Y
,
WMF
C
out
in
in
3
MDR
,
IR
out
in
4
R3
,
MAR
,
Read
out
in
5
R1
,
Y
,
WMF
C
out
in
6
MDR
,
SelectY,
Add,
Z
out
in
7
Z
,
R1
,
End
out
in
instruction
Add
(R3),R1.
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Branch
Add
T
T
4
6
T
1
Figure 7.12. Generation of the Zin control signal
for the processor in Figure 7.1.
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