System Software (CS 54)

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System Software (CS 54)
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Outline

• Introduction
• System software machine architecture
• The Simplified Instructional Computer (SIC) (Sec.
  1.3)
• Traditional CISC Machines (Sec. 1.4)
• RISC Machines (Sec. 1.5)

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Intro

• Introduces the design implementation of system
  software
• 2 types
• Application software
• System software

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Application Software (1/2)

• Is any tool that functions is operated by
  means of a computer as a tool
• Purpose of supporting or improving the software
  users work
• Subclass of computer software
• Employs the capabilities of computer directly to
  a dedicated task that the user wishes to perform
  
• Focus on the application

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Application Software (2/2)

• Types
• Word processing S/W
• MS word, Notepad, WordPad
• Database S/W
• Oracle, MS Access
• Spreadsheet S/W
• Excel, Lotus, Apple Numbers
• Multimedia S/W
• Real Player, Media Player
• Presentation Graphics S/W
• MS PowerPoint

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System Software (1/7)

• Set of programs that supports the operation of a
  computer
• Acts as an intermediary b/w computer hardware
  application programs
• Controls the computer system enhances its
  performance
• Focus is on the system

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System Software (2/7)

• Examples
• Text Editor
• Compiler
• Loader / Linker
• Debugger
• Assembler
• Interpreter

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System Software (3/7)

• Text Editor
• Allows user to create/modify a file having only
  plain text
• Edit contents to get an immediate visual feedback
• Emacs (Unix)
• Notepad (Microsoft)
• SimpleText, TextEdit (Mac OS)

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System Software (4/7)

• Compiler
• Higher language to assembly language
• Translates source code into data, that computer
  can understand
• Source code to object code
• ADA, BASIC, Fortran, Pascal
• C, C, C
• Open Source, Research

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System Software (5/7)

• Linker
• Object code from compiler is turned into
  executable program
• Gathers 1 or more objects generated by the
  compiler combines into a single EXE
• In IBM OS/360 termed as linkage editor
• Loader
• Loads programs from executables into memory
  executes

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System Software (6/7)

• Debugger
• Tests debugs errors
• Code run on Instruction Set Simulator (ISS)
• Step by step
• Breakpoint
• DEBUG Microsoft DOS built-in debugger
• Nemiver Graphical C/C debugger
• Ups Fortran, C
• VB Watch Visual Basic
• Jswat Open source Java
• Xdebug PHP

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System Software (7/7)

• Assembler
• Assembly language to machine language
• Mnemonics to machine code
• Produces executable machine code
• Pattern of bits
• Interpreter
• High level language to machine language
• Executes immediately

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System S/W Machine Architecture (1/2)

• Main characteristic is MACHINE DEPENDENCY
• Machine Dependent
• Machine Independent
• Application Program
• Concerned with solution of problem, using
  computer as tool
• Focus on application
• Not on the computing system

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System S/W Machine Architecture (2/2)

• System program
• Supports the operation use of computer
• Focus on system
• Machine dependent
• Machine Independent
• Some aspects of system software, do not directly
  depend upon the type of computing system
• general design logic of an assembler
• general design logic of a compiler
• code optimization techniques

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The Simplified Instructional Computer (SIC) (1/2)

• Hypothetical computer that includes the hardware
  features most often found on real machines
• Why SIC?
• Not to get embroiled in the idiosyncrasies of any
  particular machine.
• Understand system software at a generic level.

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The Simplified Instructional Computer (SIC) (2/2)

• Two versions of SIC
• SIC
• SIC/XE (extra equipments or extra expensive)
• SIC program can be executed on SIC/XE (upward
  compatible)
• Upward compatible
• Object program for the standard SIC machine will
  execute properly on SIC/XE system

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SIC Machine Architecture (1/7)

• Memory
• Registers
• Data formats
• Instruction formats
• Addressing Modes
• Instruction Set
• Input Output

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SIC Machine Architecture (2/7)

• Memory
• 215 bytes memory
• 32,768 bytes
• 8-bit bytes
• 3 consecutive bytes form a word (24 bits)
• Little endian
• addressed by location of lowest numbered byte
• Least significant part of a numeric value is
  stored at the lowest numbered address

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SIC Machine Architecture (3/7)

• Registers
• 5 registers each of length 24 bits

Register Number Function Use
A 0 Accumulator Arithmetic operations
X 1 Index register Addressing
L 2 Linkage register Storing return address for subroutine jumps (JSUB)
PC 8 Program counter Address of next instruction to be fetched
SW 9 Status word Flags, other information including Condition Code (CC)
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SIC Machine Architecture (4/7)

• Data Formats
• Integers are stored as 24-bit binary numbers
• 2s complement for negative values
• 8-bit ASCII for characters
• No floating point hardware in standard SIC
• Instruction Formats
• 24-bit format
• x indicates indexed addressing mode
• 8 1 15

opcode X address
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SIC Machine Architecture (5/7)

• Addressing modes
• 2 addressing modes available
• Indicated by x bit in the instruction
• () indicates the contents of a register or a
  memory location
• (x) represents the contents of register x

Mode Indication Target address calculation
Direct x 0 TA address
Indexed x 1 TA address (x)
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SIC Machine Architecture (6/7)

• Instruction Set
• Load and store LDA, LDX, STA, STX etc
• Integer arithmetic operations ADD, SUB, MUL, DIV
• All arithmetic operations involve register A and
  a word in memory, with the result being left in
  the register
• Comparison COMP
• COMP compares the value in register A with a word
  in memory, this instruction sets a condition code
  CC to indicate the result
• Conditional jump instructions JLT, JEQ, JGT
• these instructions test the setting of CC and
  jump accordingly
• Subroutine linkage JSUB, RSUB
• JSUB jumps to the subroutine, placing the return
  address in register L
• RSUB returns by jumping to the address contained
  in register L

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SIC Machine Architecture (7/7)

• Input Output
• Input and output are performed by transferring 1
  byte at a time to or from the rightmost 8 bits of
  register A
• The Test Device (TD) instruction tests whether
  the addressed device is ready to send or receive
  a byte of data
• Less Than if device is ready Equal if
  device is busy.
• Read Data (RD)
• read a byte from the device to register A
• Write Data (WD)
• write a byte from register A to the device

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SIC/XE Machine Architecture (1/12)

• Memory
• Larger Memory
• 220 bytes (1 megabyte) in the computer memory
• Leads to change in instruction formats
  addressing modes
• Registers
• Additional registers provided

Mnemonic Number Use
B 3 Base register used for addressing
S 4 General working register no special use
T 5 General working register no special use
F 6 Floating point accumulator (48 bits)
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SIC/XE Machine Architecture (2/12)

• Data Formats
• Floating-point data type frac2(exp-1024)
• fraction 01
• exponent 02047
• 1 11 36
• Sign is indicated by s (0 ve, 1 -ve)

s exponent fraction
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SIC/XE Machine Architecture (3/12)
Formats 1 and 2 do not reference memory at all
Instruction Formats
8
opcode
Format 1 (1 byte)
8 4 4
opcode r1 r2
Format 2 (2 bytes)
6 1 1 1 1 1 1 12
opcode n i x b p e disp
Format 3 (3 bytes)
e 0
6 1 1 1 1 1 1 20
opcode n i x b p e address
Format 4 (4 bytes)
e 1
Bit e distinguishes between formats 3 and 4 Large
memory extends addressing capacity
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SIC/XE Machine Architecture (4/12)

• Addressing modes
• Base relative (n1, i1, b1, p0)
• Program-counter relative (n1, i1, b0, p1)
• Direct (n1, i1, b0, p0)
• Immediate (n0, i1, x0)
• Indirect (n1, i0, x0)
• Indexing (both n i 0 or 1, x1)
• Extended (e1)
• Note Indexing cannot be used with immediate or
  indirect addressing

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SIC/XE Machine Architecture (5/12)

• Base Relative Addressing Mode

n i x b p e
opcode 1 1 1 0 disp
n1, i1, b1, p0 TA(B)disp (0?disp
?4095)

• Program-Counter Relative Addressing Mode

n i x b p e
opcode 1 1 0 1 disp
n1, i1, b0, p1 TA(PC)disp (-2048?disp
?2047)
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SIC/XE Machine Architecture (6/12)

• Direct Addressing Mode

n i x b p e
opcode 1 1 0 0 disp
n1, i1, b0, p0 TAdisp (0?disp
?4095)
n i x b p e
opcode 1 1 1 0 0 disp
n1, i1, b0, p0 TA(X)disp
(with index addressing mode)
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SIC/XE Machine Architecture (7/12)

• Immediate Addressing Mode

n i x b p e
opcode 0 1 0 disp
n0, i1, x0 TA disp

• Indirect Addressing Mode

n i x b p e
opcode 1 0 0 disp
n1, i0, x0 TA(disp)
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SIC/XE Machine Architecture (8/12)

• Simple Addressing Mode

n i x b p e
opcode 0 0 disp
i0, n0 TAb/p/e/disp (SIC
standard)
n i x b p e
opcode 1 1 disp
i1, n1 TAdisp (SIC/XE
standard)
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SIC/XE Machine Architecture (9/12)
For formats 3 and 4

• Immediate addressing mode (n 0, i 1)
• The target address is used as the operand
• Indirect addressing mode (n 1, i 0)
• The word at the location given by the target
  address is fetched
• The value contained in this word is then used as
  the address of the operand value
• Simple addressing mode
• The target address is taken as the location of
  the operand
• (n 1, i 1) used by SIC/XE
• (n 0, i 0) used by SIC

Indexed addressing cannot be used with immediate
or indirect modes.
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SIC/XE Machine Architecture (10/12)
4 Format 4 instruction D Direct-addressing
instruction (i.e.,)non-relative addressing b0
p0 A Assembler selects either program-counter
relative or base- relative mode S Compatible
with instruction format for standard SIC
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PC-relative simple addressing (PC)
disp Base-relative indexed simple addressing (B)
disp (X) PC-relative indirect addressing
(PC) disp Immediate addressing disp SIC simple
addressing b/p/e disp Simple addressing addr
All of these instructions are LDA.
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SIC/XE Machine Architecture (12/12)

• Instruction Set
• new registers LDB, STB, etc.
• floating-point arithmetic ADDF, SUBF, MULF, DIVF
• register move RMO
• register-register arithmetic ADDR, SUBR, MULR,
  DIVR
• supervisor call SVC
• generates an interrupt for OS
• Input / Output
• SIO, TIO, HIO
• start, test, halt the operation of I/O device

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Complete Instruction Set (1/5)
P privileged instruction X available
only on XE F floating- point
Instruction C condition code CC set to
indicate result of operation
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Complete Instruction Set (2/5)
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Complete Instruction Set (3/5)
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Complete Instruction Set (4/5)
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Complete Instruction Set (5/5)
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SIC SIC/XE Programming Examples(1/10)
WORD Integer constant
BYTE Character constant
Immediate addressing makes the program run faster
because it need not fetch five from the memory.
RESB - Reserve indicated number of bytes for a
data area
RESW - Reserve indicated number of words for a
data area
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SIC SIC/XE Programming Examples(2/10)
BETA (ALPHA INCR - 1) DELTA (GAMMA
INCR - 1)
Fig Arithmetic operations SIC
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SIC SIC/XE Programming Examples(3/10)
BETA (ALPHA INCR - 1) DELTA (GAMMA
INCR - 1)
This program will execute faster because it need
not load INCR from memory each time when INCR is
needed.
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SIC SIC/XE Programming Examples(4/10)

• During 1st loop exec, T.A. for LDCH will be
  address of 1st byte of STR1
• llly STCH stores copied character into 1st byte
  of STR2
• TIX 2 operations
• adds 1 to value in register X
• compares new value in register X to value of
  operand

Fig Looping and indexing SIC

• Loop copies 11 bit character string to another

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SIC SIC/XE Programming Examples(5/10)

• Same as TIX. Value for comparison is taken form
  another register, not from memory
• Loop efficient, bcoz value not fetched from
  memory each time the loop is executed

Will execute faster because TIXR need not compare
the index value to a memory variable
Fig Looping and indexing SIC/XE
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SIC SIC/XE Programming Examples(6/10)

• Loop is cumbersome, bcoz register A is used for
  adding array elements for incrementing the
  index value

Gamma Alpha Beta
Fig Looping indexing SIC
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SIC SIC/XE Programming Examples(7/10)
This program will execute faster because it uses
register-to-register add to reduce memory
accesses.
Fig Looping indexing SIC/XE
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SIC SIC/XE Programming Examples(8/10)

• Reads 1byte from device F1 copies to device 05
• Operand for RD is a byte in memory, containing
  the hexadecimal code for input device
• Executing RD transfers 1byte data from device F1
  to Right Most Byte of register A
• Before RD is executed, input device must be
  ready to transmit, by checking TD instruction
• When TD is executed, status of addressed device
  is tested condition code set to indicate
  result.
• If device ready, CC is less than, else equal

• Output too performed the same way
• 1st TD checks, if O/P device is ready to receive
  a byte
• Byte written into Right Most Byte of register A
• WD to transmit data to device

Fig
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SIC SIC/XE Programming Examples(9/10)

• Read operation placed in a subroutine
• Subroutine called from main using JSUB
• At end of subroutine, RSUB, returns control to
  instruction following JSUB
• READ subroutine consists of loop
• TD, CC, then RD

Read 100 byte record into buffer

• TIX 2 operations
• adds 1 to value in register X
• compares new value in register X to value of
  operand

Fig Subroutine call record input operations SIC
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SIC SIC/XE Programming Examples(10/10)

• Immediate addressing
• TIXR instruction

TIXR makes this program run faster
Fig Subroutine call record input operations
SIC/XE
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Diverse Architectures

• Traditional (CISC) machines
• VAX architecture
• Pentium Pro architecture
• RISC machines
• Ultra SPARC architecture
• PowerPC architecture
• Cray T3E architecture

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Traditional (CISC) Machines

• Complex Instruction Set Computers (CISC)
• Complicated instruction set
• Different instruction formats and lengths
• Many different addressing modes
• Implementation in h/w complex

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VAX Architecture (1/10)

• Introduced by Digital Equipment Corporation (DEC)
  in 1978
• Compatible with earlier PDP-11 machines
• DECs 1st only 16 bit microcomputer in 1970
• Compatibility mode provided at h/w level, to run
  vice versa
• Possible for PDP-11 and VAX programs to share
  same machine in multi-user environment

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VAX Architecture (2/10)

• Characteristics
• Memory
• Registers
• Data Formats
• Instruction Formats
• Addressing Modes
• Instruction Set
• Input

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VAX Architecture (3/10)

• Memory
• 8-bit bytes
• word (2 bytes)
• longword (4 bytes)
• quadword (8 bytes)
• octaword (16 bytes)
• Virtual address space (232 bytes)
• Allows programs to operate as if having access to
  extremely large memory
• Half of virtual address space System space
• Contains the operating system
• Shared by all programs
• Other half of virtual address space Process
  space
• Defined separately for each program
• Contains stacks, available to program
• Special registers machine instructions aid in
  the use of stacks

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VAX Architecture (4/10)

• Registers
• 16 general purpose registers Processor Status
  Longword(PSL)
• R0 R15
• 32 bits length
• R15 program counter (PC)
• points to next instruction byte to be fetched
• R14 stack pointer (SP)
• points to current top of stack in programs
  process space
• R13 frame pointer (FP)
• address of procedure call, placed in stack frame
  pointed by FP
• R12 argument pointer (AP)
• procedure call uses AP to pass arguments
  associated with call
• R6 R11 (no special functions, general use)
• R0 R5 (general use, but used by some machine
  instructions)
• Processor Status Longword (PSL)
• contains state variables flags associated with
  a process

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VAX Architecture (5/10)

• Data Formats
• Integers stored as binary in byte, word,
  longword, quadword or octaword
• 2s complement for negative values
• Characters by 8-bit ASCII codes
• 4 different floating point data formats (4 - 16
  bytes length)
• 2 of these compatible with PDP-11 standard on
  all VAX processors
• Other two available as options
• Provide packed decimal data format
• Each byte represents 2 decimal digits, with each
  digit encoded using 4 bits of the byte
• Sign encoded in last 4 bits
• Numeric data format
• Represents numeric values with one digit per byte
• Sign may appear either in last byte or as a
  separate byte preceding the 1st digit
• These 2 variations are called trailing numeric
  and leading separate numeric.

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VAX Architecture (6/10)

• Instruction Formats
• Use variable length instruction format
• Each instruction has an operation code (1 or 2
  bytes) followed by 6 operand specifiers,
  depending on instruction
• Each operand specifier designates one of the VAX
  addressing modes

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VAX Architecture (7/10)

• Addressing Modes
• Register mode
• Operand itself may be in a register
• (Eg) LOAD Reg1, Reg2
• Reg1 (Reg2)
• Register deferred mode (register indirect mode)
• Address of operand in memory is stored in one of
  the registers
• (Eg) LOAD Reg1, (Reg2)
• Reg1 Mem(Reg2)
• Autoincrement mode / Autodecrement mode
• If the operand address is in a register, the
  register contents may be automatically
  incremented or decremented by the operand length
• (Eg) LOAD Reg1, (Reg2)
• Reg1 Mem(Reg2) Reg2 (Reg2)
  step
• (Eg) LOAD Reg1, - (Reg2)
• Reg1 (Reg2) step Reg1
  Mem(Reg2)

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VAX Architecture (8/10)

• Addressing Modes
• Program-counter relative mode
• When displacement is added to program counter(PC)
• Branches / jumps using this are advantageous
• Immediate mode
• If the operand is part of the instruction
• (Eg) LOAD Reg1, const
• Reg1 const
• Direct mode (absolute mode)
• Address of operand in memory is stored in the
  instruction
• (Eg) LOAD Reg1, (const)
• Reg1 Memconst

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VAX Architecture (9/10)

• Instruction Set
• Symmetric with respect to data type
• Prefix specifies the type of operation
• Suffix specifies the data type of operands
• Modifier gives number of operands involved
• (Eg) ADDW2 add operation with 2 operands,
  each a word in length
• MULL3 multiply operation with 3 longword
• CVTWL conversion from word to longword
• Operands may be in registers, memory or
  instruction itself
• Provides instructions for computation, data
  movement conversion, comparison, branching etc.
• Provides instructions to load and store multiple
  registers

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VAX Architecture (10/10)

• Input Output
• Accomplished by I/O device controllers
• Each controller has a set of control/status
  data registers, which are assigned locations in
  the physical address space
• I/O space
• Portion of address space into which the device
  controller registers are mapped
• Software routines and memory management routines
  are used

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Pentium Pro Architecture (1/6)

• Introduced in 1995, last of Intel x86 family
• Majority of PCs vast amount of software for
  these
• Memory
• Registers
• Data Formats
• Instruction Formats
• Addressing modes
• Instruction set
• Input Output

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Pentium Pro Architecture (2/6)

• Memory
• 8 bit bytes, all addresses used are byte
  addresses
• 2 bytes (word), 4bytes (doubleword or dword)
• Viewed as collection of segments
• Address consists of 2 parts
• Segment number offset that points to a byte
  within the segment
• Segments store executable instructions data
• Data segments treated as stacks
• Used to save register contents, pass parameters
  to subroutines
• Segment also divided into pages
• Some reside in physical memory also stored in
  disk
• MMU translates segment/offset address into
  physical byte address

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Pentium Pro Architecture (3/6)

• Registers
• 32 bit long, 8 general purpose registers
• EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP
• EAX, EBX, ECX, EDX for data manipulation
• Others used to hold addresses
• EIP 32 bit, has a pointer to the next to be
  exec. Instr
• FLAGS 32 bit, has many different bit flags
• Indicate processors status, records result of
  arithmetic/comparison operations
• Six 16 bit registers CS, DS, ES, FS, GS, SS
• Used to locate segments in memory
• CS address of currently executing code segment
• SS address of current stack segment
• Floating Point Unit performs computations
• Eight 80-bit data registers and other control
  status registers

66
Pentium Pro Architecture (4/6)

• Data Formats
• Integers 8, 16, 32 bit binary numbers
• Supports signed / unsigned integers
• FPU handles 64 bit signed integers
• 2s comp for ve numbers
• Integers also stored in Binary Coded Decimal
  (BCD)
• Unpacked BCD each byte represents one decimal
  digit
• Packed BCD each byte represents two decimal
  digits
• 3 floating point data formats
• Single precision 32 bits long
• 24 (significant bits) 7 (exponent) 1 (sign)
• Double precision 64 bits long
• 53 10 1
• Extended precision 80 bits long
• 64 15 1
• Characters one per byte, 8-bit ASCII codes
• Strings Bits, Bytes, Words, Doublewords

67
Pentium Pro Architecture (5/6)

• Instruction Formats
• Use prefixes to specify repetition count
• Following prefix(if present), is an opcode (1 or
  2 bytes), then number of bytes to specify
  operands, addressing modes
• Varies in length from 1 10 bytes
• Opcode always present in every instruction
• Addressing modes
• Immediate mode, register mode, direct mode,
  relative mode
• Use of base register with displacement is also
  possible

68
Pentium Pro Architecture (6/6)

• Instruction Set
• Large complex 400 different machine
  instructions
• Each instruction can have 0,1,2 or 3 operands
• Reg-reg, reg-mem, mem-mem instructions
• Input Output
• Input is from an I/O port into register EAX
• Output from EAX to I/O port

69
RISC Machines (1/2)

• Reduced Instruction Set Computers (RISC)
• Instruction
• Standard, fixed instruction length
• Single-cycle execution of most instructions
• Memory access is available only for load and
  store instruction
• Other instructions are register-to-register
  operations
• A small number of machine instructions, and
  instruction format
• A large number of general-purpose registers
• A small number of addressing modes

70
RISC Machines (2/2)

• SPARC family
• UltraSPARC
• PowerPC family
• Cray T3E

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UltraSPARC Architecture (1/5)

• Sun Microsystems in 1995
• Scalable Processor ARChitecture
• Ultra SPARC Super SPARC
• Wise range from microcomputers to supercomputers
• Upward compatible share same basic structure
• Memory
• 8-bit bytes
• halfword (2 bytes)
• word (4 bytes)
• doubleword (8 bytes)
• Virtual address space of 264 bytes, divided into
  pages
• Some reside in physical memory others

72
UltraSPARC Architecture (2/5)

• Registers
• Large register file 100 Gen.Pur reg with 64
  bits length
• Only 32 reg (r0 r31) are accessible
• r0 r7 global
• r0 always has value zero
• Other 24 reg can be visualized as window
  overlap
• Reg (r8-r15) of calling procedure, physically
  same as reg (r24-r31) of called procedure
• Floating Point Unit (FPU)
• 64 double precision floating point reg
• Has PC, condition code registers number of
  control registers

73
UltraSPARC Architecture (3/5)

• Data Formats
• Integers 8, 16, 32, 64 bit binary numbers
• Supports signed / unsigned integers
• 2s comp for ve numbers
• Both big-endian little-endian
• 3 floating point data formats
• Single precision 32 bits long
• 23 (significant bits) 8 (exponent) 1 (sign)
• Double precision 64 bits long
• 52 11 1
• Quad precision 80 bits long
• 63 15
• Characters one per byte, 8-bit ASCII codes

74
UltraSPARC Architecture (4/5)

• Instruction Formats
• 32 bits long three basic formats
• 1st two bits identify the format
• Format 1 for call instruction
• Format 2 for branch instruction
• Format 3 for load, store arithmetic
  operations
• Addressing Modes
• Immediate operand value part of instruction
• Register direct operand value may be in a
  register
• Operands in memory addressed by 3 modes
• PC relative
• TA (PC) displacement
• Register indirect with displacement
• TA (register) displacement
• Register indirect indexed
• TA (register - 1) (register - 2)

75
UltraSPARC Architecture (5/5)

• Instruction Set
• Fewer than 100 instructions
• Only instruction accessing memory load store
• Others are Reg-Reg operations
• Pipelined execution
• One when executed, the next gets fetched from
  memory decoded
• Speeds up instruction execution
• Input and Output
• Communication with I/O devices is accomplished
  through memory
• Range of memory locations is logically replaced
  by device registers
• When load/store instruction refers to this device
  register area of memory, the corresponding device
  is activated

76
PowerPC Architecture (1/5)

• IBM introduced POWER in 1990
• Performance Optimization With Enhanced RISC
• IBM, Apple, Motorola in 1991 founded PowerPC
• Memory
• 8-bit bytes
• halfword (2 bytes)
• word (4 bytes)
• doubleword (8 bytes)
• quadword (16 bytes)
• Virtual address space of 264 bytes, divided into
  segments, 256 MB long
• Segment partitioned into pages, 4096 bytes long
• Some reside in physical memory also stored in
  disk

77
PowerPC Architecture (2/5)

• Registers
• 32 gen pur registers 64 bits long
• Used to store manipulate integer data
  addresses
• FPU has 32 (64-bit) floating point registers
  a status control register
• 32 bit condition register to testing branching
• Link register (LR), Count register (CR) branch
  instructions
• Machine Status register(MSR)

78
PowerPC Architecture (3/5)

• Data Formats
• Integers 8, 16, 32, 64 bit binary numbers
• Supports signed / unsigned integers
• 2s comp for ve numbers
• Both big-endian little-endian
• Little-endian by setting a bit in the control
  register
• 2 floating point data formats
• Single precision 32 bits long
• 23 (significant bits) 8 (exponent) 1 (sign)
• Double precision 64 bits long
• 52 11 1
• Characters one per byte, 8-bit ASCII codes

79
PowerPC Architecture (4/5)

• Instruction Formats
• 7 formats
• 32 bits long
• Addressing modes
• Immediate operand value part of instruction
• Register direct operand value may be in a
  register
• Load store operations use these 3 modes
• Register indirect
• TA (register)
• Register indirect with index
• TA (register-1) (register-2)
• Register indirect with immediate index
• TA (register) displacement
• Link register
• TA (LR)
• Count register
• TA (CR)

80
PowerPC Architecture (5/5)

• Instruction Set
• 200 machine instructions approx.
• Input and Output
• 2 methods for performing I/O operations
• Segments in the virtual address space are mapped
  onto an external address space
• Such segments are called direct-store segments

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CRAY T3E Architecture (1/4)

• Announced by Cray Research Inc., 1995
• Massively Parallel Processing (MPP), contains
  large number of processing elements (PE),
  arranged in a 3-dimensional network
• Each PE consists of a DEC Alpha EV5 RISC
  processor, local memory
• Has 16 to 2048 processing elements
• Memory
• Each PE has its own local memory with capacity
  from 64 MB to 2 GB
• 8-bit bytes
• word (2 bytes)
• longword (4 bytes)
• quadword (8 bytes)

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Cray T3E Architecture (2/4)

• Registers
• 32 GPRs 64 bit length R0 through R31
• R31 always has value zero
• 64 bit program counter, status control
  registers
• Data Formats
• Integers long quadword binary numbers
• 2s comp for negative numbers
• Supports little-endian ordering
• 2 floating point formats
• VAX IEEE
• Characters 8 bit ASCII

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Cray T3E Architecture (3/4)

• Instruction Formats
• 32 bit long, five instruction formats
• 1st 6 bits always identify the opcode
• Addressing Modes
• Immediate mode - operand value part of
  instruction
• Register-direct mode - operand value may be in a
  register
• PC-relative
• TA (PC) displacement
• In conditional unconditional branches
• Register indirect with displacement
• TA (register) displacement
• Load store operations

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Cray T3E Architecture (4/4)

• Instruction Set
• 130 machine instructions approx.
• No byte or word load store instructions
• Input and Output
• Communication accomplished through multiple ports
  into one or more I/O channels
• Channels are integrated into the network that
  interconnects the processing nodes
• All channels are accessible and controllable from
  all PEs