Precision Timed PRET Architecture

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Precision Timed (PRET) Architecture

• Hiren D. Patel, Ben Lickly, Isaac Liu and Edward
  A. Lee
• hiren,blickly,liuisaac,eal_at_eecs.berkeley.edu
• University of California, Berkeley

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Timing Properties in Computing Abstractions
Programming models and languages

• Most traditional computing abstractions hide
  timing properties of software
• Advantages
• Focus on functionality
• Push for higher average-case performance
• Disadvantages
• Real-time embedded systems
• Unpredictable
• Non-repeatable
• Brittle

Multithreading
Compilers, and ISAs
Speculative execution, caches, and deep pipelines
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Resulting Real-time Embedded Systems

• Unpredictability
• Difficulty in determining timing behavior through
  analysis
• Non-repeatability
• Different executions may yield different timing
  behavior
• Brittleness
• Small changes have big effects on timing behavior

Time as a first class citizen of embedded
computing
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Precision Timed (PRET) Architectures
Predictable and repeatable timing
Stephen. A. Edwards and Edward. A. Lee, The case
for the Precision Timed (PRET) machine. In
Proceedings of the 44th Annual Conference on
Design Automation (San Diego, California, June 04
- 08, 2007). DAC '07. ACM, New York, NY, 264-265.
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Precision Timed Architecture
ISA with timing instructions
Scratchpad memories
Round-robin thread scheduling
Thread-interleaved pipeline
Time-triggered arbitration
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Timing Instructions Deadline

• ISA extensions
• dead Ip Edwards in 2006
• deadload
• Deadline instructions
• Denote the required execution time of a block
• When decoded
• Stall instruction until timer value is 0
• Then set timer value to new value

Block 1
Block 2
Block 3
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Timing Instructions Exceptions

• ISA extensions
• deadbranch
• deadloadbranch
• What happens when missing deadlines?
• Raise exception and perform pre-specified actions

To control timing behaviors in software, we need
a predictable underlying architecture
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Pipeline Architecture with Predictable Timing
Traditional pipeline
Stall pipeline
Dependencies result in complex timing behaviors
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Thread-interleaved Pipeline with Timing
Instructions
Decrement deadline timers

• Thread stalls
• Main memory access
• Deadline instructions
• Replay mechanism
• Execute same PC next iteration

Stall if deadline instruction
If not stalled, increment PC
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Memory Hierarchy with Predictable Timing

• Scratchpad memories
• Software managed caches

Each thread has a uniquely defined address space
1 cycle latency
Shared data goes through to main memory
Predictable timing behavior during cache accesses
13 cycles latency
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Time-triggered Access to Main Memory

• Each thread must make and complete access within
  its window

• Memory wheel
• Time-triggered access

Worst-case bound on access time 136 12 90
cycles
Predictable timing behavior when accessing main
memory
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Examples

• Video rendering for a computer game
• Real-time requirements through deadline
  instructions
• Autonomous robot finding moving target
• Anytime algorithms using timing exceptions
• Eliminating time-exploiting attacks in
  cryptosystems
• Repeatable timing behavior through deadline
  instructions

RSA Encryption (RSAREF 2.0)
DSA Encryption from OpenSSL (0.9.8j)
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Predictable Timing and High Performance
Code generation from Giotto, SDF, and PTIDES.
Timing analysis
Real-time network on-chip
Programming models and languages with time
semantics
PRET Machine
Scratchpad memory allocation schemes
Thread scheduling and synchronizations
Multi-PRET architecture
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Conclusion

• Treat time as a first class property of embedded
  computing
• Predictable and repeatable timing behaviors
• PRET cycle-accurate simulator
• ISA extensions with timing instructions
• Architecture with predictable timing behaviors
• Download http//chess.eecs.berkeley.edu/pret/

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End