3' EQUATION SIMPLIFICATION

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• 3. EQUATION SIMPLIFICATION
• It is a direct method using postulates
  and theorem of a Boolean algebra enable
  the manipulations of a formula into
  equivalent forms.
• Example ( x x y) ( x y) y z
• 4. THE REDUCTION THEOREM
• For the purpose of obtaining simple
  Boolean formula two additional theorems are
  useful,

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• These theorems are known as Shannons
  reduction theorems.
• theorem 3
• xi f( x1, x2, ..xi..xn) xi f( x1, x2,
  ..1..xn)
• xi f( x1, x2, ..xi..xn) xi f( x1, x2,
  ..0..xn)
• Where f( x1, x2, ..k,..xn) for k 0,1.
• Similarly
• xi f( x1, x2, ..xi..xn) xi f( x1, x2,
  ..0..xn)
• xi f( x1, x2, ..xi..xn) xi f( x1, x2,
  ..1..xn)
• Where f( x1, x2, ..k,..xn) for k 0,1.
• Example f(w,x,y,z) x x y w x ( w z) (
  y w z )

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• 5. MINTERM CANONICAL FORMULA
• 1. Apply DeMorgans law a sufficient no. of
  times until all the
• NOT operations appear only with
  the single variables.
• 2. Apply distributive of AND over OR ()
  over ()
• i.e. x(yz) xyxz in order to
  manipulate the formula
• into disjunctive normal formula.
• 3. Remove duplicate literals and turns by
  idempotent law well as
• any term that are identically
  zero (xx 0)
• 4. If any product in the disjunctive
  normal formula does not
• contain all the variables of the
  Boolean function then these
• missing variables are introduced
  by ANDing the terms with
• logic 1 in the form of xixi
  where xi is the missing variable being
• introduced. This process is
  repeated for each missing variables in
• each of the product turns of the
  disjunctive normal form

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• 5. Apply distributive of ( ) over () again
  so that each
• variable appears exactly once in
  each term.
• 6. Remove duplicate term if any.
• Example ( x y) ( y x z )( x
  y)

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• 6. MAXTERM CANONICAL FORMULA
• 1. Apply DeMorgans law until all the NOT
  operations appear with single variables.
• 2. Apply distributive law of () over ()
• i.e. (xyz) (xy)(xz) and bring the
  expressions into its conjugate normal form
  (POS).
• 3. The missing variables are introduced
  into the sum terms by OR ing logic 0s in
  the form xi xi 0 where xi is missing
  variable.
• 4. Distributive law of () over () is again
  applied.
• 5. Duplicate literals are deleted.
• Ex f(x,y,z) ( x y ) ( y x z )( x y )

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• 7. COMPEMENTS OF CANONICAL FORMULAS
• Even by taking complements minterm
  expression may result different expressions.
• Ex f(x,y,z) ?m(0, 2, 4, 6) its complement
  expression is
• f(x,y,z) ?m(1, 3, 5,7)
• Similarly
• A Maxterm canonical expression may be
  represented in completed for as follows
• Ex f(x,y,z) ? M (1, 2, 4, 7) its complement
  expression is
• f(x,y,z) ? M (0 3, 5,6)

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• GATES AND COMBINATIONAL NETWORKS
• Gates are electronics circuits whose terminal
  characteristics correspond to the various
  Boolean operations. Where as logic
  networks is a network of interconnections of
  gates and flip flops. The gates are
  operated with two possible steady state
  voltage signal values appear at the
  terminals of the circuits at any time.
• An electronic circuit in which the output
  signal is a logic-1 if and only if all
  its inputs are at logic-1 is called AND
  gate.

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• An electronic circuit in which the output
  signal is a logic-1 if and only if at
  least one of its input signal is at
  logic-1 is called OR gate.
• 3. An electronic circuit in which the
  output signal is always opposite logic with
  input signal is called as NOT gate or
  inverter gate.

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• COMBINATIONAL NETWORKS

x1 x2 - xn
z1 Z2 - zm
Combinational network
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• 1. COMBINATIONAL NETWORK
• The inter connections 0f gates result in
  a gate network. If the network has the
  property that its outputs at any time are
  determined strictly by the inputs at that
  time then the network is said to be a
  combinational network. Ex. Adders.
  Multiplexers. etc
• Let us consider an set of n signals at
  any time is called input state or input
  vector of the network. While a set of
  resulting signals appearing at the m output
  terminals is called the output state or
  output vector. The network can be expressed
  as

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• z1, z2,zm as Boolean function then
• Zi fi(x1,x2,.xn) for i 1,2,m.
• 2. SEQUENTIAL NETWORKS
• A second type of logic network is the
  sequential networks. Sequential network have
  memory property, so that the the outputs
  from these networks are dependent not only
  upon the current inputs but upon previous
  input as well. Feed back path are used in
  the sequential circuits. Ex. Counters. Shift
  registers etc.

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• ANALYSIS PROCEDURE
• Analysis procedure for a combinational
  network is as follows
• 1. Each gate output that is only a function
  of the input variables is labeled.
• 2. Boolean algebraic expression for the
  outputs of each of these gates are then
  written.

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• 3. Next these gates outputs that are a
  function of just inputs variables and
  previously labeled gate outputs.
• 4. Then each of the previously defined
  labels is replaced by the already written
  Boolean expression and this process is
  continued until the output of the network
  is labeled and till final expression is
  obtained.

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• f(w,x,y,z) w(yz) wxy
• wG1 G2
• f(w,x,y,z) G2 G3

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• SYNTHESIS PROCEDURE
• The synthesis procedure or logic design will
  be obtained by having specification of the
  desired behavior of a gate network. The
  truth table will provide total information
  of network specifications. If the variables
  and their compliments are used as inputs
  then such logic is said to be DOUBLE RAIL
  logic. If the variables and their
  complements are not available, then
  not-gates are required then it is called
  SINGLE RAIL logic.
• The gate input signals will pass through
  input to out is called as levels of logic.

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• Example1 f(w,x,y,z) w x x (yz)
• In the above logic circuit their exists 3-
  logic levels G1, G2 G3 with double -rail
  logic.
• Example 2 f(w,x,y,z) w x x y x z
• In the above logic circuit there exists two
  level logic levels with double -rail.

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• INCOMPLETE BOOLEAN FUNCTION WITH DONOT CARE
  CONDITIONS
• In this type of Boolean functions having
  n-variables so that it may have 2n
  combinations of subsets and if all values
  are not specified such functions are called
  incompletely specified functions.
• Ex. Let us consider a three variable
  function with following truth table

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• We can describe the incomplete function in
  the SOP form as
• f(x,y,z) ?m(0,1,7) dc(3,5)
• Also we can represent the function in the
  pos form as
• f(x,y,z) ?M(2,4,6) dc(3,5)
• The odd parity generation result output
  expression
• f(w,x,y,z) ?m(0,3,5,6,9) dc(10,11,12,13,14,15)
• f(w,x,y,z)w x y z x y z x y z x y z w z

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• ADDITIONAL BOOLEAN OPERATIONS AND GATES
• The NAND and NOR gates are referred as
  universal gates or universal building
  blocks.
• 1. NAND FUNCTION
• nand(x1, x2, .xn) (x1,x2,.. xn)
• Ay applying DeMorgans law we get
• x1, x2,..xn x1x2.xn

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• NAND- GATE REALIZATIONS
• Any Boolean functions can be realized by
  nand gates alone
• 1. Apply DeMorgans law to the expression to
  obtain in unary operation i.e. appear only
  with single variables. Draw the logic diagram
  using and and-or gates.
• 2. Replace each and gate symbol by nand-gate
  and each or-gate symbol by nand-gates.
• 3. Check for bubbles occurring on all lines
  between two gate symbols. so that two gates
  will be there.

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• 4. Whenever an input variable enters a gate
  symbol at a bubble then Complement the
  variable of the gate. If the output has
  a bubble then insert an output not-gate
  symbol.
• 5. Replace all not-gates by a nand-gate
  equivalent if desired.
• Example f(w,x,y,z) w z w z ( x y)

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• 2. NOR FUNCTION
• nor(x1, x2, .xn) (x1x2..xn)
• Ay applying DeMorgans law we get
• x1x2.xn x1, x2,..xn

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• NOR-GATE REALIZATIONS
• To realize an Boolean function we must
  follow the procedure listed below
• 1. Apply DeMorgans law to the expression to
  obtain expression in unary operations i.e.
  appear only with single variables. Draw the
  logic diagram using and and-or gates.
• 2. Replace each or gate symbol by nor-gate
  and each and-gate symbol by nor-gates
  symbol.
• 3. Check for bubbles occurring on all lines
  between two gate symbols. so that two gates
  will be there.

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• 4. Whenever an input variable enters a gate
  symbol at a bubble then Complement the
  variable of the gate. If the output has
  a bubble then insert an output not-gate
  symbol.
• 5. Replace all not-gates by a nand-gate
  equivalent if desired.
• Example f(w,x,y,z) w z w z ( x y)

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• EX-OR FUNCTION
• A EX-OR gate will have two input and a
  output. The EX-OR gate will be logic 1 if
  and only if both inputs are not at same
  logic state.
• The Boolean output expression of EX-OR
  gate is
• f1 x y x y
• f2 ( x y )( x y )
• f3 x y x y
• f4 (x y ) (x y)

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• The truth table of Ex-OR gate

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• EX-NOR FUNCTION
• A EX-NOR gate will have two input and a
  output. The EX-NOR gate will be logic 1 if
  and only if both inputs are at same logic
  state.
• The Boolean output expression of EX-NOR
  gate is
• f1 x y x y
• f2 ( x y )( x y )
• f3 x y x y
• f4 ( x y ) (x y)

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• The truth table of Ex-NOR gate