Auburn%20University

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Pipeline Processor Design Project Jarred Beck
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Design Assumptions

• Three bit opcode
• This is to be able to address all of the 8k
  memory directly. 213 8192
• 16 registers with some limitations
• In certain formats, only the first 8 are able to
  reached
• Two reserved registers for the lw and sw.

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Design Assumptions Cont.

• Pipeline Data Path Structure
• Ease of testability. (theoretically)
• Fast.
• Compiler responsibilitys
• Hazard Prevention.
• Lw and Sw data moving.
• Jump return.

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Register List
Register Register Description
zero 0 Holds constant zero value
a0 1 Holds an argument value
a1 2 Holds an argument value
a2 3 Holds an argument value
t0 4 Holds an argument value
t1 5 Holds a temporary value
s0 6 Holds a saved value
lr 7 Last value loaded from memory
sr 8 Last value stored into memory
s0 9 Holds a saved value
s1 10 Holds a saved value
t2 11 Holds a saved value
t3 12 Holds a saved value
ra 13 Holds the return
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Instruction Set
Instruction Set Formats Instruction Set Formats Instruction Set Formats Instruction Set Formats Instruction Set Formats Instruction Set Formats
Inst. Type Format Format Format Format Format
  Opcode Result Reg. Argument 1 Argument 2 ALU Op
Arithmatic (A) XXX XXXX XXXX XXX XX
           
  Opcode Compare Reg. 1 Compare Reg. 2 Direction Branch Offset
Branch (Br) XXX XXX XXX X XXXXXX
           
  Opcode Address Address Address Address
Jump (J) XXX XXXXXXXXXXXXX XXXXXXXXXXXXX XXXXXXXXXXXXX XXXXXXXXXXXXX
           
  Opcode Address Address Address Address
Memory (M) XXX XXXXXXXXXXXXX XXXXXXXXXXXXX XXXXXXXXXXXXX XXXXXXXXXXXXX
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Instruction Set Cont.
Opcode Instructions
 
Arithmatic
Jump (J)
Load Word (Lw)
Store Word (Sw)
Nop
Hlt
Beq
Bneq
 
has sub opcodes
Instructions
Add
Sub
And
Or
Beq
Bneq
j
lw
sw
hlt
nop
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Control Unit

• 11 bits wide.
• Controls include
• Branch Flags
• Jump Flag
• Data Memory Read and Write Flags
• Register Write Flag
• Mux controls for Memory Input, Register Input,
  and Register Address

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Control Unit Cont.
Control Bit Function
10 Jump Flag
9 BEQ Flag
8 Data Read
7 Data Write
6 Data Select
5 Reg Write Sel.
4 BNEQ Flag
3 Reg Write
2 PC Write
1 Branch Signal
0 LW Addr Sel
Opcode Instructions Control Pattern
   
Arithmatic 00000001100
Jump (J) 10000000101
Load Word (Lw) 00100101100
Store Word (Sw) 00011000100
Nop 00000000100
Hlt 00000000000
Beq 01000000110
Bneq 00000010110
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Datapath
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Simulation Results

• Individual Components
• All Components passed tests
• Datapath and CPU
• Datapath Passed tests
• Control Unit Passed test
• Memory passed
• Top level CPU problems

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Moving Forward

• Debug Top level VHDL
• Altera passes compilation
• ModelSim gives error
• Synthesize corrected version into board

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Questions?

• The End