Environmental Simulation of Circuit Board Epoxy

1
Environmental Simulation of Circuit Board Epoxy

• Group Members
• Greg Kurtz
• Brad Walsh
• Brad Grimmel
• Jeff Baudek

2
Project Overview

• Lockheed/Martin is having a problem with cracking
  in circuit boards and circuit board epoxy
• Project involves
• Repairing an environmental chamber
• Duplicating the cracking through physical testing
• Using FEA/FEM to model circuit boards
• Proposing a solution

3
Environmental Chamber

• Must cycle temperature from 50C to 80C in one
  hour

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Repairs Made to Chamber

• Replaced Blower motor
• Selected and Purchased new controller
• Rewired LN2 solenoid and cables between chamber
  and controller
• Made new wiring diagrams for operator references
• Had new 208V 40A power outlet installed in NHMFL

5
Testing of Repaired Chamber

• Chamber was cycled through maximum range of 73C
  to 316C
• Chamber is capable of completing diurnal cycle
  from 50C to 80C in less than one hour

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Circuit Board Testing

• Purpose of testing was to simulate the effect of
  the standard military diurnal cycle on a UR-329
  encapsulated circuit board

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Preparation Procedure

1. Heat mold to 100C and apply releasing agent
2. Mix resin and hardener and insert into vacuum
   chamber (samples were also prepared without
   vacuum)
3. Curing period (either normal or accelerated cure)

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Physical Testing

• Samples were then cycled between 50 deg C and 80
  deg C each hour
• Samples were checked approximately every 25
  cycles
• Samples were exposed to approximately 550 cycles
  during testing

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SEM Untreated Samples
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SEM thermally cycled sample
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Results of Testing

• Cracking in epoxy

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Results of Testing (Contd)

• Cracking in circuit board

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Finite Element Analysis (FEA)

• 2-D and 3-D models made using FEA programs Ansys
  and Algor
• Assumptions
• Uniform Temperature Distribution
• Constraint of zero displacement at two corners
• Constant Material Properties

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FEA Schematics
2-D
3-D
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2-D Ansys Model
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3-D Ansys Model
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3-D Algor Model
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Results of FEA

• 2-D Ansys model showed stresses that were below
  the yield point of the circuit board
• 3-D Ansys model was inaccurate due to constraints
• 3-D Algor model showed that the stress present in
  the circuit board was below the yield point

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Thermal Stress Calculations

• Axial and Bending Stress due to temperature
  variations in the circuit board and epoxy were
  done to supplement the FEA

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Model Setup
Basic Equations

• Assumed
• Constant value of E and CTE
• Epoxy delaminated from the circuit board
• Uniform temperature distribution

DL LoaDT
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UR-329 Elastic Modulus
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UR-329 Coefficient of Thermal Expansion
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Results of Calculations

• Calculated Axial stresses were below the yield
  stress of the ceramic throughout the entire
  temperature range
• Calculations determined that with a constant CTE
  of 191.710-6/C an Elastic Modulus of 4230 psi
  for the epoxy is needed to crack the circuit
  board due to bending stress which occurs within
  the diurnal cycle specified by Lockheed/Martin
  for testing

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Summary

• Repair of Environmental Chamber
• Recreation of circuit board and epoxy cracking
  through physical testing and observed using SEM
• FEA was completed
• Thermal stress calculations revealed that circuit
  board should crack

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Recommendations

• Use epoxy with
• A modulus of elasticity with a lower glass
  transition temperature
• A decreasing coefficient of thermal expansion
  with decreasing temperature
• Further investigation of
• Fatigue properties of circuit board
• Adhesive properties of the epoxy
• Examine use of different epoxy fillers