EE201C Chapter 3 Interconnect RLC Modeling

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EE201C Chapter 3 Interconnect RLC Modeling

• Prof. Lei He
• LHE_at_ee.ucla.edu

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Chapter 3 Interconnect RLC Model

• Efficient capacitance model
• Efficient inductance model
• RC and RLC circuit model generation

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Reading Assignments

• J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali
  and S. H.-C. Yen, "Analysis and Justification of
  a Simple, Practical 2 1/2-D Capacitance
  Extraction Methodology", ACM/IEEE Design
  Automation Conference, June 1997, pp.627-632
• http//eda.ee.ucla.edu/pub/c7.pdf
• L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An
  Efficient Inductance Modeling for On-chip
  Interconnects", (nomination for Best Paper
  Award)IEEE Custom Integrated Circuits Conference,
  San Diego, CA, pp. 457-460, May 1999.
• http//eda.ee.ucla.edu/pub/c11.pdf
• M. Xu and L. He, "An efficient model for
  frequency-based on-chip inductance," IEEE/ACM
  International Great Lakes Symposium on VLSI, West
  Lafayette, Indiana, pp. 115-120, March 2001.
• http//eda.ee.ucla.edu/pub/c18.pdf

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Is RC Model still Sufficient?

• Interconnect impedance is more than resistance
• Z ? R j?L
• ? ? 1/tr
• On-chip inductance should be considered
• When ?L becomes comparable to R as we move
  towards Ghz designs

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Candidates for On-Chip Inductance

• Wide clock trees
• Skews are different under RLC and RC models
• Neighboring signals are disturbed due to large
  clock di/dt noise
• Fast edge rate (100ps) buses
• RC model under-estimates crosstalk
• P/G grids (and C4 bumps)
• di/dt noise might overweight IR drop

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Resistance vs Inductance
Length 2000, Width 0.8 Thickness 2.0,
Space 0.8
Ls and Lx for two parallel wires
R and ?L for a single wire
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Impact of Inductance
6000u
10u
5u
5u
Gnd
Gnd
Clk
RC model
RLC model
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Inductance Extraction from Geometries

• Numerical method based on Maxwells equations
• Accurate, but way too slow for iterative physical
  design and verification
• Efficient yet accurate models
• Coplanar bus structure He-Chang-Shen-et al,
  CICC99
• Strip-lines and micro-strip bus lines
  Chang-Shen-He-et al, DATE2K
• Used in HP for state-of-the-art CPU design

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Definition of Loop Inductance
Ii
Ij
Vj
Vi

• The loop inductance is

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Loop Inductance for N Traces
Tw
TwL
TwR
Tw
Tw
Ts
Ts
TsL
TsR
tL
t1
t2
t3
tR
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Table in Brute-Force Way is Expensive
Tw
Tw
TwL
TwR
Tw
1.73 1.15 0.53 1.15 1.94 1.24 0.53 1.24
1.92
Ts
Ts
TsL
TsR
tL
t1
t2
t3
tR

• Self inductance has nine dimensions
• (n, length, location,TwL,TsL,Tw,Ts,TwR,TsR)
• Mutual inductance has ten dimensions
• (n, length, location1, location2,TwL,TsL,Tw,Ts,Tw
  R,TsR)
• Length is needed because inductance is not
  linearly scalable

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Definition of Partial Inductance
Vj
Vi

• Partial inductance is the portion of loop
  inductance for a segment when its current returns
  via the infinity
• called partial element equivalent circuit (PEEC)
  model
• If current is uniform (no skin effect), the
  partial inductance is

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Partial Inductance for N Traces
Tw
Tw
TwL
TwR
Tw
6.17 5.43 5.12 4.89 4.66 5.43 6.79 6.10
5.48 5.04 5.12 6.10 6.79 6.10 5.33 4.89
5.48 6.10 6.79 5.77 4.66 5.04 5.33 5.77
6.50
Ts
Ts
TsL
TsR
tL
t1
t2
t3
tR

• Treat edge traces same as inner traces
• lead to 5x5 partial inductance table
• Partial inductance model is more accurate
  compared to loop inductance model
• Without pre-setting current return loop

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Foundation I

• The self inductance under the PEEC model for a
  trace depends only on the trace itself (w/ skin
  effect for a given frequency).

Tw
TwL
TwR
Tw
Tw
Ts
Ts
TsL
TsR
tL
t1
t2
t3
tR
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Foundation II

• The mutual inductance under the PEEC model for
  two traces depends only on the traces themselves
  (w/ skin effect for given frequency).

Tw
TwL
TwR
Tw
Tw
Ts
Ts
TsL
TsR
tL
t1
t2
t3
tR
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Foundation III

• The self loop inductance for a trace on top of a
  ground plane depends only on the trace itself
  (its length, width, and thickness)

Tw
Tw
TwL
TwR
Tw
4.8 2.5 1.3 0.7 0.14 2.5 5.5 2.9 1.5
0.7 1.3 2.9 5.7 2.9 1.3 0.7 1.5 2.9
2.5 2.5 0.14 0.7 1.3 2.5 4.8
Ts
Ts
TsL
TsR
t1
t2
t3
tR
tL
4.8
tR
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Foundation IV

• The mutual loop inductance for two traces on top
  of a ground plane depends only on the two traces
  themselves (their lengths, widths, and thickness)

Tw
TwL
TwR
Tw
Tw
4.8 2.5 1.3 0.7 0.14 2.5 5.5 2.9 1.5
0.7 1.3 2.9 5.7 2.9 1.3 0.7 1.5 2.9
2.5 2.5 0.14 0.7 1.3 2.5 4.8
Ts
Ts
TsL
TsR
tL
t1
t2
t3
tR
0.14
4.8
tL
tR
4.8
0.14
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Validation and Implication of Foundations

• Foundations I and II can be validated
  theoretically
• Foundations III and IV were verified
  experimentally

• Problem size of inductance extraction can be
  greatly reduced w/o loss of accuracy
• Solve 1-trace problem for self inductance
• Reduce 9-D table to 2-D table
• Solve 2-trace problem for mutual inductance
• Reduce 10-D table to 3-D table

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Analytical Solutions to Inductance
Not suitable for on-chip interconnects

• Without considering skin effect and internal
  inductance
• Self inductance
• kf(w,t) 0 lt k lt 0.0025
• Mutual inductance

• Inductance is not sensitive to width, thickness
  and spacing
• No need to consider process variations for
  inductance

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Extension to Random Nets Xu-HE, GLSVLSI01

• Mutual inductance Lab

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Accuracy

• Table versus FastHenry
• 400 random displaced parallel wires cases

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Error Distribution

• ?5 most cases
• Bigger error only found in smaller inductance
  values

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Full RLC Circuit Model
Ls(wire12)
Self inductance L11 N11 N12 val L12
N13 N14 val L21 N21 N22 val L22 N23 N24
val mutual inductance K1 L11 L21
val K2 L12 L22 val K3 L11 L12 val K4
L21 L22 val K5 L11 L22 val K6 L21 L12
val
N13
N11
N14
N12
N23
N21
N24
N22

• For n wire segments per net
• RC elements n
• self inductance n
• mutual inductance n(n-1)

Lm(wire21, wire12) / sqrt(L21 L12)
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Normalized RLC Circuit Model
Ls(net1)
Self inductance L11 N11 N12 val L12
N13 N14 val L21 N21 N22 val L22 N23 N24
val mutual inductance K1 L11 L21
val K2 L12 L22 val
N13
N11
N14
N12
N23
N21
N24
N22
Lm(net1, net2) / sqrt(net1 net2)

• For n segments per wire
• RC elements n
• Self inductance n
• Mutual inductance n

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Full Versus Normalized

• Two waveforms are almost identical
• Running time
• Full 99.0 seconds
• Normalized 9.1 seconds

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Application of RLC modelShielding Insertion

• To decide a uniform shielding structure for a
  given wide bus
• Ns number of signal traces between two
  shielding traces
• Ws width of shielding traces

Ws
Ws
Ws
...
...
1
2
3
1
2
Ns
3
Ns
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Trade-off between Area and Noise

• Total 18 signal traces
• 2000um long, 0.8um wide
• separated by 0.8um
• Drivers -- 130x Receivers -- 40x
• Power supply 1.3V

Ns Ws Noise(v) Routing Area (um) Wire Area (um)
18 -- 0.71 61.1(0.0) 46.4(0.0) 6 0.8 0.38 64.
8 48.0 6 1.6 0.27 66.4 49.6 6 2.4 0.22 68.0
51.2 3 0.8 0.17 69.6(13) 50.4(8.8)
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Conclusions

• Inductance is a long-range effect
• Inductance can be extracted efficiently use PEEC
  model
• Normalized RLC circuit model with a much reduced
  complexity can be used for buses
• Full RLC circuit model should be used for random
  nets
• Model reduction or sparse inductance model may
  reduce circuit complexity
• RLC circuit model may be simulated for
  interconnect optimization