VIP

1
NCTU, CS
VLSI Information Processing
Research Lab
Low-Cost Graphics Processor
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• ABSTRACT
• Introduction
• NEW Recursive DFT/IDFT architecture
• Low computation cycle
• 1/2 Chebyshev polynomial
• 2/N Folded architecture
• High speed
• Register-splitting and computation-sharing scheme
• New Recursive Formula For DFT/IDFT

• The Proposed Folded Type DFT/IDFT Architecture

In this work,

• Data Buffer
• 64 16-bit word length complex data storage
• Control Unit
• Clock Gated Control
• Sequence Controller
• Parameter Controller
• 32 PEs32 PEs
• Pre-processing for Sk and rk
• TWO PEs for DST and DCT

• Proposed two design
• Core Type N2/2
• Folded Architecture N

• Regularity construct by the N/2 PEs in parallel
• No intermediate register bank needed
• Further reduce the computation cycle to N
• N (N2/2) / (N/2)
• Processor latency 64 clock
• (Computation cycles)
• Critical Path Tm2Ta

,where

• Simulation and Implementation Results
• Lower round of error due to the fewest
  computation cycle
• AWGN Channel

• 212/106-point recursive DFT/IDFT Design
• For DTMF Detector System

DFT Length (N)
Input Word Length
Critical Delay Time
Active Chip Area
Power Consumption
Process Technology
The Proposed Recursive DFT formula

Comparisons Results
Parameters Second Order DFT/IDFT V-Ys Structure 4 (Core Type) Y-Cs Structure 6 (FFR-DFT) Proposed Work1 (Core Type) Proposed Work2 (Folded Type)




The Proposed Recursive IDFT formula

• Conclusion
• A new recursive DFT/IDFT architecture based on
  the hybrid of Input strength reduction, Chebyshev
  polynomial and register-splitting schemes is
  proposed.
• The proposed VLSI algorithms lead to the fewest
  computation cycle and higher speed than others.
• The proposed core type and folding type recursive
  architecture with regular organization is
  certainly amenable to VLSI implementation.

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The Proposed Core-Type DFT Architecture
The Proposed Core-Type IDFT Architecture
Achieve
Cost Speed