Logic Gate Delay Modeling -1

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Logic Gate Delay Modeling -1

• Bishnu Prasad Das
• Research Scholar
• CEDT, IISc, Bangalore
• bpdas_at_cedt.iisc.ernet.in

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OUTLINE

• Motivation
• Delay Model History
• Delay Definition
• Types of Models
• -RC delay Models
• -Logical Effort
• Limitation of Logical Effort
• Summary

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Motivation

• Why Model is required?
• For fast simulation
• Solving differential equation is difficult
• For creating optimal design
• Real design will be always more costly and time
  consuming.So model is used to simulate the system
  before actual implementation.

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Types of Models

• Physical Models
• Based on Physical phenomena of device
• Empirical Models
• Based on curve fitting ( i.e. Quadratic,Cubic
  etc.)
• No physical significance.
• Table Models
• Storing the data in a Lookup Table
• Do interpolation between stored data

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Delay Model History
Courtesy Synopsys
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Delay Definitions

• tpdr rising propagation delay
• From input to rising output crossing VDD/2
• tpdf falling propagation delay
• From input to falling output crossing VDD/2
• tpd average propagation delay
• tpd (tpdr tpdf)/2
• tr rise slew
• From output crossing 0.2 VDD to 0.8 VDD
• tf fall slew
• From output crossing 0.8 VDD to 0.2 VDD

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Delay Definitions

• tcdr rising contamination delay
• From input to rising output crossing VDD/2
• tcdf falling contamination delay
• From input to falling output crossing VDD/2
• tcd average contamination delay
• tpd (tcdr tcdf)/2

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Delay Definitions

• tpdr rising propagation delay
• From input to rising output crossing VDD/2
• tpdf falling propagation delay
• From input to falling output crossing VDD/2
• tpd average propagation delay
• tpd (tpdr tpdf)/2
• tr rise time
• From output crossing 0.2 VDD to 0.8 VDD
• tf fall time
• From output crossing 0.8 VDD to 0.2 VDD

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Delay Definitions

• tcdr rising contamination delay
• From input to rising output crossing VDD/2
• tcdf falling contamination delay
• From input to falling output crossing VDD/2
• tcd average contamination delay
• tpd (tcdr tcdf)/2

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RC Delay Models

• Use equivalent circuits for MOS transistors
• Ideal switch capacitance and ON resistance
• Unit nMOS has resistance R, capacitance C
• Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width

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Example 3-input NAND

• Sketch a 3-input NAND with transistor widths
  chosen to achieve effective rise and fall
  resistances equal to a unit inverter (R).

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Example 3-input NAND

• Sketch a 3-input NAND with transistor widths
  chosen to achieve effective rise and fall
  resistances equal to a unit inverter (R).

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Example 3-input NAND

• Sketch a 3-input NAND with transistor widths
  chosen to achieve effective rise and fall
  resistances equal to a unit inverter (R).

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3-input NAND Caps

• Annotate the 3-input NAND gate with gate and
  diffusion capacitance.

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3-input NAND Caps

• Annotate the 3-input NAND gate with gate and
  diffusion capacitance.

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3-input NAND Caps

• Annotate the 3-input NAND gate with gate and
  diffusion capacitance.

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Elmore Delay

• ON transistors look like resistors
• Pullup or pulldown network modeled as RC ladder
• Elmore delay of RC ladder

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Example 2-input NAND

• Estimate worst-case rising and falling delay of
  2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate worst-case rising and falling delay of
  2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Delay Components

• Delay has two parts
• Parasitic delay
• 6 or 7 RC
• Independent of load
• Effort delay
• 4h RC
• Proportional to load capacitance

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Contamination Delay

• Best-case (contamination) delay can be
  substantially less than propagation delay.
• Ex If both inputs fall simultaneously

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Layout Comparison

• Which layout is better?

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Delay in a Logic Gate

• Express delays in process-independent unit
• Delay has two components
• f is due to external loading
• p is due to self loading

t 3RC FO1 delay without parasitic delay
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Delay in a Logic Gate

• Express delays in process-independent unit
• Delay has two components
• Effort delay f gh (a.k.a. stage effort)
• Again has two components

t 3RC FO1 delay without parasitic delay
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Delay in a Logic Gate

• Express delays in process-independent unit
• Delay has two components
• Effort delay f gh (a.k.a. stage effort)
• Again has two components
• g logical effort
• Measures relative ability of gate to deliver
  current
• g ? 1 for inverter

t 3RC FO1 delay without parasitic delay
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Delay in a Logic Gate

• Express delays in process-independent unit
• Delay has two components
• Effort delay f gh (a.k.a. stage effort)
• Again has two components
• h electrical effort Cout / Cin
• Ratio of output to input capacitance
• Sometimes called fanout

t 3RC FO1 delay without parasitic delay
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Delay in a Logic Gate

• Express delays in process-independent unit
• Delay has two components
• Parasitic delay p
• Represents delay of gate driving no load
• Set by internal parasitic capacitance

t 3RC FO1 delay without parasitic delay
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Effort Delay

• Logical Effort g Cingate/Cin_unit_inv
• Electrical Effort h Cout / Cingate
• f gh (Cingate/Cin_unit_inv)(Cout /
  Cingate)
• (Cout / Cin_unit_inv)
• (Dactual)ext gh t (Cout /
  Cin_unit_inv)3RC
• (Cout /
  Cin_unit_inv)RCin_unit_inv
  CoutR

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Computing Logical Effort

• DEF Logical effort is the ratio of the input
  capacitance of a gate to the input capacitance of
  an inverter delivering the same output current.
• Measure from delay vs. fanout plots
• Or estimate by counting transistor widths

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Catalog of Gates

• Logical effort of common gates

Gate type Number of inputs Number of inputs Number of inputs Number of inputs Number of inputs
Gate type 1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n2)/3
NOR 5/3 7/3 9/3 (2n1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8
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Catalog of Gates

• Parasitic delay of common gates
• In multiples of pinv (?1)

Gate type Number of inputs Number of inputs Number of inputs Number of inputs Number of inputs
Gate type 1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate / mux 2 4 6 8 2n
XOR, XNOR 4 6 8
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Delay Plots

• d f p
• gh p

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Delay Plots

• d f p
• gh p
• What about
• NOR2?

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Example Ring Oscillator

• Estimate the frequency of an N-stage ring
  oscillator
• Logical Effort g
• Electrical Effort h
• Parasitic Delay p
• Stage Delay d
• Frequency fosc

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Example Ring Oscillator

• Estimate the frequency of an N-stage ring
  oscillator
• Logical Effort g 1
• Electrical Effort h 1
• Parasitic Delay p 1
• Stage Delay d 2
• Frequency fosc 1/(2Nd) 1/4N

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Example FO4 Inverter

• Estimate the delay of a fanout-of-4 (FO4)
  inverter
• Logical Effort g
• Electrical Effort h
• Parasitic Delay p
• Stage Delay d

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Example FO4 Inverter

• Estimate the delay of a fanout-of-4 (FO4)
  inverter
• Logical Effort g 1
• Electrical Effort h 4
• Parasitic Delay p 1
• Stage Delay d 5

The FO4 delay is about 200 ps in 0.6 mm
process 60 ps in a 180 nm process f/3 ns in
an f mm process
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Multistage Logic Networks
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Limits of Logical Effort

• Chicken and egg problem
• Need path to compute G
• But dont know number of stages without G
• Simplistic delay model
• Neglects input rise time effects
• Interconnect
• Iteration required in designs with wire
• Maximum speed only
• Not minimum area/power for constrained delay

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Summary

• RC Delay Model
• Delay measurement using Logical Effort Method
• Gate sizing using Logical Effort for minimum
  delay
• Limitations of Logical Effort

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Reference

• N. H. E. Weste and D. Harris, CMOS VLSI Design,
  A circuits and Systems Perspective 3rd edition
  Pearson Addison Wesley
• Rabaey, Chandrakasan and Nikolic, Digital
  Integrated Circuits, a Design Perspective,
  Pearson Education