Physikalisches Institut UNI-Heidelberg

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Physikalisches InstitutUNI-Heidelberg
Venelin Angelov Elektronikwerkstatt
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Digital system design with FPGA

• Logic Box
• SUbmodules available
• Some Designs
• 7x100 MHz ADC
• Dual MALU
• TDC
• The new DL711 Logic Box
• The new ADC SUBmodule

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Logic Box

• Block Diagram
• USB Interface
• User Design
• Top Contraints Generator
• Design Flow

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Block Diagram of DL701/6/9
bytes
DL701/6 xc3s400 DL709/10 xc3s4000 DL711
xc6slx150t
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User Design
User I/Os
read port
CDin
MS bits of CAddr
write port
CWR
CDout
MS bits of CAddr
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Generate Top and UCF files
specifiy the DL7xx type
gen_lb DL709 -s2 SU704 -s3 SU736 -t
../../SRC/TOP/DL709.vhd -o top.vhd -u top.ucf
specifiy the SU7xx cards
specifiy the template file
specifiy the VHDL output file
specifiy the UCF output file
This program supports now DL701, 706, 709, 710,
711 SU701, 702, 703, 704, 706, 707, 709, 710,
711, 712, 713, 714, 715, 717, 720, 721,
722, 724, 725, 726, 727, 728, 730, 731,
733, 734, 736, 737
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SUbmodules overview
SU701 TTL I/O 16 channels in two groups SU702 8
channel 14-bit ADC (MAX1149) SU703 4 channel fast
dicriminator with 2xMAX9601 (dual PECL
comparator) 2xMAX537 (4x serial DAC) SU704 5
channel TTL or NIM I/O SU705 4M x 16-bit
RAM SU706 100 MS/s 14-bit ADC (ADS5500) SU707 8
channel LVDS I/O SU709 8 temperature sensors
SMT160-30 / HY-LINE 16092 SU710 2 channel 14-bit
DAC SU711 Delay SU712 Dual 8 channel 14-bit ADC
(MAX1149), like SU720 but without isolation SU713
Dual 8 channel 14-bit DAC SU714 ADC ADS5500 SU715
2 channel audio preamplifier SU716 16M x 32-bit
RAM SU717 Gated integrator with ADS5500 SU720
Dual 8 channel 14-bit ADC (MAX1149), like SU712
but with isolation
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SUbmodules overview
SU721 Dual 8 channel 14-bit DAC, like SU713 but
with isolation SU722 5 channel TTL I/O, like
SU700 but with isolation SU724 Toslink
interface SU725 8 channel ECL input SU726 32
LEDs SU727 Toslink interface SU728 16-bit ADC and
DAC SU730 PSRAM 8M x 16 bit SU731 4 x H-Bridge,
36V 2A SU733 Optical In/Out SU734 DDS Modul with
AD9910 SU735 100 MS/s 14-bit ADC SU736 2 channel
fast dicriminator with programmable threshold
hysteresis and direct NIM outputs (1xMAX9600
dual ECL comparator AD5624 4x serial
DAC) SU737 Optical Gigabit Ethernet with TLK2201
(SerDes) and SFP Module
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7x100 MHz ADC Design
7 x 100 MHz 14-bit ADC SUbmodules 1 x 5 TTL/NIM
IO Submodule Multievent buffering 4 events _at_
2048 samples 512 events _at_ 16 samples Programmab
le presample length USB2.0 Interface C, C or
LabView
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TOP BLOCK DIAGRAM
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ADC CLOCK
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ADC SPI INTERFACE
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ADC CLOCK ADJUST 100 MHz
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ADC DATA PATH
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EVENT DATA FORMAT
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OPERATION
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Dual MALU

• 32 inputs, NIM or TTL (selectable at each input)
• Two logical groups consisting of user
  programmable subset of the 32 inputs
• In each group
• Delay gate generators at each input (100 MHz)
• Four outputs
• 3 of them just discriminators with programmable
  thresholds
• one implemented as pattern checker
• Counters at each input and output for debugging

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Block Diagram
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Input edge detection and mask
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DGG, Discriminator Pattern Cheker
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Pattern Cheker
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TDC
Based on DL709 2 x SU704 (5xNIM/TTL) - 7
channels (start 0..6) and stop, TTL/NIM - 2.5 ns
resolution - Event builder with timestamp -
Multievent buffering - USB2.0 readout, C, C or
LabView (Windows)
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DL711

• As DL709
• - Spartan 6 FPGA XC6SLX150t with SerDes
• Two SFPs
• DRAM
• SDCARD slot
• Interface (now USB2.0) as mezzanine card
• 8 slots for SUbmodule Cards

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SU735
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SU735 Prototype
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SU735 Ver1
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EW _at_ PI UNI-HD (2009)
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EW _at_ PI UNI-HD (2013)
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Thank You
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SPARESAusstattung
at KIP
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Generate Top and UCF files
library IEEE use IEEE.std_LOGIC_1164.ALL use
work.LogicBox_pkg.all entity DL709 is Port (
CLK in std_logic RES_n
in std_logic LED_Back
out std_logic -- put here the
signals to the SUxxx modules -- Slot 0 is
empty -- Slot 1 is empty -- SU704 on slot 2
SU2_INTTL in std_logic_vector( 5
downto 1) SU2_OUTP out
std_logic_vector( 5 downto 1) SU2_INECL
in std_logic_vector( 5 downto 1)
SU2_OE_n out std_logic_vector( 5
downto 1) SU2_LED_n out
std_logic_vector( 5 downto 1) SU2_TERM
out std_logic_vector( 5 downto 1)
Clock, Reset and LED
SU7xx boards
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Generate Top and UCF files
-- SU736 on slot 3 SU3_CMP_SE in
std_logic_vector( 2 downto 1) ...
SU3_SDO_DAC in std_logic
SU3_SCLK_DAC out std_logic
SU3_CS_DACn out std_logic ...
-- end of the SUxxx section -- FX2 FXClk
out std_logic FXAddr
out std_logic_vector( 1 downto 0)
FXData inout std_logic_vector(
7 downto 0) FXRD_n out
std_logic ... FXPEnd_n out
std_logic) end DL709
SU7xx boards
USB Interface
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Generate Top and UCF files
Component declaration
component top_core is Generic(ClkMHz integer
100) Port ( CLK in
std_logic Reset in
std_logic -- put here the signals to the
SUxxx modules -- Slot 0 is empty -- Slot 1 is
empty -- SU704 on slot 2 SU2_INTTL
in std_logic_vector( 5 downto 1) ...
SU2_TERM out std_logic_vector( 5
downto 1) -- SU736 on slot 3 SU3_CMP_SE
in std_logic_vector( 2 downto
1) ... SU3_LED_NIMn out
std_logic_vector( 2 downto 1) -- IF CAddr
in std_logic_vector(31 downto
0) CWR in std_logic
CRD in std_logic
CDIn in std_logic_vector(31
downto 0) CDOut out
std_logic_vector(31 downto 0) CRdy
out std_logic) end component
SU7xx signals
CBus signals
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Generate Top and UCF files
DL709 NET "CLK"
LOC "AF14" IOSTANDARD LVTTL NET
"LED_Back" LOC "K26"
IOSTANDARD LVTTL NET "RES_n"
LOC "G26" IOSTANDARD LVTTL
PULLUP NET "FXRD_n"
LOC "W26" IOSTANDARD LVTTL NET "FXWR_n"
LOC "AC14"
IOSTANDARD LVTTL NET "FXEmpty"
LOC "M26" IOSTANDARD LVTTL NET
"FXFull" LOC "L26"
IOSTANDARD LVTTL NET "FXClk"
LOC "R26" IOSTANDARD LVTTL NET
"FXAddrlt0gt" LOC "Y26"
IOSTANDARD LVTTL NET "FXAddrlt1gt"
LOC "AC25" IOSTANDARD LVTTL NET
"FXSLOE_n" LOC "Y25"
IOSTANDARD LVTTL NET "FXPEnd_n"
LOC "AC26" IOSTANDARD LVTTL NET
"FXDatalt0gt" LOC "Y15"
IOSTANDARD LVTTL NET "FXDatalt7gt"
LOC "AA12" IOSTANDARD LVTTL
Empty slot 0 Empty slot 1 SU704 on slot 2 NET
"SU2_INTTLlt5gt" LOC "P1"
IOSTANDARD LVTTL NET "SU2_OUTPlt5gt"
LOC "P2" IOSTANDARD LVTTL NET
"SU2_INECLlt5gt" LOC "P3"
IOSTANDARD LVTTL NET "SU2_OE_nlt5gt"
LOC "P4" IOSTANDARD LVTTL
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Directory tree
\_ C \_ SIM \_ USB2CBUS
\_ SRC \_ DATA \_ SRC
\_ COMMON (led.vhd, ticker.vhd,
LogicBox_pkg.vhd, svn_extract.vhd ) \_
USB2CBUS \_ TOP \_ PROJECTS
\_ DL709_2xSU704_TDC \_
DL709_7xSU706 \_ DL709_8xSU704_MALU
\_ DL709_SU737_GbEth (Makefile)
\_ C
\_ SCRIPTS
\_ SRC (DL709.vhd )
\_ SIM_TOP_CORE (Makefile)
\_ SRC
\_ DATA

\_ REPORTS (cleared before
compilation) \_
other temporary
(controller_va.vhd, FX2.vhd, FTDI245n.vhd,
usb2cbus_fx2.vhd
usb2cbus_ftdi.vhd, VME2CBUS.vhd)
(Templates DL7xx.vhd)
(DL709.ucf.xst, DL709_files.txt, bitgen.ut,
xprog.cmd, xprog_flash.cmd)