GTX Update: Framework and New Studies

1
GTX UpdateFramework and New Studies

• Dirk Stroobandt
• Ghent University / UCLA

2
Outline

• Introduction
• New additions and developments
• New studies
• Model analysis
• Study of the impact of parameters
• Design optimization studies
• Future plans

3
GTX GSRC Technology Extrapolation System

• GTX is set up as a framework for technology
  extrapolation

4
New Implementation Developments

• Engine extensions
• Support for name spaces (as in C) currently
  being implemented
• Allows to attach parameter names to a specific
  module/study
• GUI extensions
• Runs on three platforms (Solaris, Windows and
  Linux)
• Batch mode for automatic testing, scripting and
  macro recording
• User support
• Software to automatically check parameter naming

5
New Data and Models

• New device and power modules (Synopsys /
  Berkeley)
• New SOI device model (Synopsys / Berkeley)
• Inductance models (Silicon Graphics / Berkeley /
  Synopsys)
• Integration of GENESYS in GTX (with help from
  Georgia Inst. Tech.)
• Integration of RIPE in GTX (with help from
  Rensselaer Univ.)
• Yield models (Carnegie-Mellon Univ.)

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New Studies Overview
Model analysis
Design optimization

• Comparison bulk Si versus SOI
• influence on clock
• frequency and power
• parameter sensitivity

• Wire sizing

• Inductance
• RC versus RLC models
• effect on wire sizing
• load capacitance model
• wire shielding

• Repeater optimization
• repeater sizing
• placement uncertainty
• staggered repeaters

• Influence of effective load capacitance
• Via parasitics

Impact of parameters
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Bulk Si Versus SOI Device Models

• New device models for bulk Si and
  Silicon-on-Insulator (SOI) devices
• Provided by Dennis Sylvester (Synopsys) and Kevin
  Cao (UC Berkeley)
• SOI model assumes partially-depleted SOI (PD-SOI)
  technology and is based on popular BSIM3SOI
  models
• Both modules compared to BSIM3 HSPICE runs
  results match within 10
• General study
• floating body effect in PD-SOI changes in vth
  and Idsat
• calculate range of possible Idsat values
• model ignores the impact of capacitive coupling
  on body voltage
• dynamic delay (due to coupling capacitances
  between same-layer interconnects)

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Bulk Si Versus SOI Device Models (Cont.)

• Influence of device technology on clock frequency
  and power
• Best case largest Idsat (realizable due to
  floating body effect, only for SOI) and no
  effective coupling capacitance f from 1.03 GHz
  (bulk) to 1.31 GHz (SOI)
• Worst case smallest Idsat and switching factor
  of 2 867 MHz and 1.05 GHz
• Power results
• SOI 16 increase in power versus Bulk but 24
  increase in frequency

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Bulk Si Versus SOI Device Models (Cont.)

• Parameter sensitivity of both models
• Several technology related parameters are varied
  by /- 10
• SOI slightly less sensitive to input parameter
  changes
• Process spread (between best-case and worst-case)
  larger for SOI

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Influence of Effective Capacitance

• Compare use of Ceff
• against Ctot for various
• gate sizes, wire lengths
• and wire widths
• Ctot leads to 100
• overestimation of gate delay

• Total gate delay intrinsic gate delay gate
  load delay
• Resistive shielding of gate load effective
  capacitance!

Interconnect delay
Intrinsic gate delay
Gate load delay
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Influence of Effective Capacitance (Cont.)

• Gate delay increases with increasing line width
  for Ceff because the resistive shielding effect
  weakens

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Repeater Optimization

• Most commonly cited optimal buffer sizing
  expression (Bakoglu)
• In GTX
• Sweep repeater size for single stage in the chain
  
• Examine both delay and energy-delay product

2.4
Lseg
2.14 mm
WS1mm
6
2.2
WS0.5mm
2.0
5
1.8
Critical Path Delay (ns)
4
1.6
Normalized Energy-Delay Product
1.4
3
1.2
1.0
2
0.8
1
0
100
200
300
400
500
Bakoglu
Repeater Size (X min size)
optimal sizing
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Repeater Optimization (Cont.)

• Repeater placement uncertainty
• Large amount of repeaters are placed in repeater
  islands Cong et al, ICCAD99
• Segment length becomes uncertain
• Half of segments will be overdriven,
• half will be underdriven

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Repeater Optimization (Cont.)

• Staggered repeaters
• First introduced in Kahng et al, VLSI Design 99
  to reduce delay and noise

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Inductance analysis

• Five different models implemented in GTX
• Bakoglus model (RC_B)
• Alpert, Devgan and Kashyap, ISPD 2000 (RC_ADK)
• Ismail, Friedman and Neves, TCAD 19(1), 2000
  (RLC_IFN)
• Kahng and Muddu, TCAD 1997 (RLC_KM)
• Extension of Alpert, Devgan and Kashyap, ISPD
  2000 (RLC_ADK)

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Inductance analysis (Cont.)

• Effect of RLC line delay models on wire sizing
• Cong and Pan, DAC 99
• Optimal line width found by sweeping width in GTX
  for RC and RLC

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Inductance analysis (Cont.)

• Effect of Ceff for two-pole RLC line delay model

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Inductance analysis (Cont.)

• Effect of shielding
• Optimize cost function wire pitch x repeater
  size x number of repeaters
• Parameters
• width of shield and signal wires
• spacing between signal wires and from signal
  wires to shield wires
• Constraints
• delay (max. 1 ns)
• delay uncertainty (difference RC 2-pole and RLC
  delays)
• noise peak (20 of Vdd)
• max. slew rate at rep. inputs 0.5 ns
• Topologies
• No shielding (NS)
• 1 shield (1S)
• 2 shields (2S)

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Inductance analysis (Cont.)

• Effect of shielding and Ceff versus Ctot (with
  two-pole RLC delay model)

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Benefits of using GTX for studies

• Easy to add new models to the GTX framework
• Bulk device, power, SOI models
• Reuse of models already present
• BACPAC cycle time model reused
• Sweeping ability allows assessment of effects of
  changing parameters
• Influence of effective capacitance (sweep wire
  length, width etc.)
• Easy rule substitution allows comparison between
  models
• RC versus RLC models
• Constraints allow elimination of infeasible
  solutions
• Shielding study used delay and noise constraints

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Future extensions to the GTX engine

• Annotated parameters (e.g., t_cycle_locallt1gt)
• Example
• old rule computes the local cycle time
  t_cycle_local
• new rule adds clock skew t_cycle_locallt2gt
  t_cycle_locallt1gt t_skew
• Benefits
• Allows parameter updating without changing
  previous rules or renaming old parameters (not
  annotated lt0gt annotation annotation
  collapsing)
• No need for different names for different
  versions of the same parameter
• Allows the same parameter as input and output to
  the same rule
• Iteration (possibly benefits from annotations)
• Several rules are combined in a single iteration
  loop

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Future studies in GTX

• Variability studies
• Cost and yield
• Reliability
• (suggestions welcome)

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Conclusions

• New work on GTX mainly on new studies
• Bulk Si versus SOI
• Influence of effective capacitance
• Repeater optimization studies
• Inductance analysis
• Inclusion of more models will allow exponential
  growth in new studies possible in GTX
• We keep searching for experts in the field
  willing to provide new models for GTX