Medipix2 Parallel Readout System

1
Medipix2 Parallel Readout System
V. Fanti, R. Marzeddu, P. Randaccio
Dipartamento di Fisica e Sezione INFN Cagliari
4-th IWORID Amsterdam 8 12 September 2002
2
Dynamic imaging with Medipix2

• ONE CHIP
• 256x256x14 bits per frame
• 25 frames per second
• 2.3 x 107 bits per second
• 2.9 x 106 bytes per second

• EIGHT CHIPS
• 1.8 x 108 bits per second
• 2.3 x 107 bytes per second
• Serial I/O 180 MHz
• Parallel I/O 32 bit 5.7 MHz

However, the readout speed should be as high as
possible to reduce the dead time aiming to 10
DT we should reach frequencies 10 times higher.
3
The PC platform as acquisition system

• Actually the PC is the best solution for
• Acquisition
• Processing
• Visualization
• Storage
• in imaging systems.

4
PC architecture

• North Bridge (Hi speed devices) South Bridge (Low
  speed devices)
• I/O interconnect busses
• Host Bus
• Memory Bus
• AGP (Graphics)
• V-link (interbridge connection)
• ATA (Hard disks)
• PCI
• USB
• IEEE 1394 firewire
• Legacy (ISA) . obsolete

5
Computer speed
The typical processor clock frequency is 1
GHz The word length is 32 bits 4 bytes but
. the data transfer rate is not 4 Gbyte/s !

• The speed is limited by the bus clock
• Host bus (between CPU and North Bridge) 200 MHz
• Memory 200 MHz AGP(4x) 132 MHz
• ATA 100 MHz PCI 33 MHz
• ISA 8 MHz

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Maximum transfer speed(the effective one)
All values expressed in Mbytes/s
Parallel busses single mode burst mode DMA
Legacy bus 2.7 ---- 4.2
PCI bus 10 60 122
Serial busses Low speed Full speed
USB 1.1 0.2 1.5
Firewire IEEE1394a 12.5 50
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The PCI bus essentials

• Peripheral Component Interconnect (PCI)
• 32-bit multiplexed data/address bus
• Clock frequency 33 MHz (66 MHz)
• Maximum (theo) transfer rate 132 MB/s (264
  MB/s)
• 3.3V 5V operability
• Plug and Play
• single mode e burst mode transaction
• reflected wave switching

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Transmission lineStandard method incident wave
switching
VME, ISA, EISA, . busses
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PCI method reflected wave switching
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PCI bus length limit
d
T_prop ? 10 ns d bus length v 2 108 m/s
Worst case ?x 2d ?x v T_prop 2 m d ? 1 m
(theo)
Tprop 30 ns Tval Tsu - Tskew
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Bridge
Connection between PCI bus and local bus
for timing, operating voltage (5V/3.3V/2.2V),
protocols
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PLX PCI9054 Bus Master I/O Accelerator
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Bridge PLX9054

• Bus Master interface
• 32-bit data bus, 28-bit address bus
• 3.3V, 5V tolerant
• Local bus clock up to 50 MHz
• Dual DMA channels
• Six Read/Write FIFOs 16 Lword
• Single and burst mode operation (block transfer
  up to 16 LWord)
• Unlimited burst length
• Memory spaces remap (up to 256 Mbytes of memory)

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Burst read mode
Local Bus
PCI Bus
Read FIFO (16 x 32 bit)
PCI Read Request
The bridge prefetches data from Local Bus device
at max. clock speed Prefetched data is stored
in the internal FIFO PCI bus reads data from the
FIFO The PCI bridge returns data from internal
FIFO in sequential address read operations until
FIFO is empty
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I/O burst advantage
Bus access (address, data, control cycles) slows
down I/O operation. The prefetch with FIFOs
reduces the time needed for bus access operations
by a factor 16. CPU reads data directly from FIFO
at very high speed.
PCI Bus
Local Bus
PCI/Local bridge
CPU
North bridge
FIFO
FIFO
Host memory
South Bridge
Host/PCI bridge
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Reading data from Medipix2 parallel port
PCI bridge reads 16 Lword from Medipix2 parallel
port through local bus
CPU reads data from FIFO
Acquisition rate is about 64 MByte/s 32 bits - 16
MHz mean acquisition rate
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Most PCs do not support burst read !
If the North Bridge has no FIFO (Intel bridges)
the CPU readout phase is slower
Acquisition rate is about 10 MByte/s
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Reading from a PCI device
4 G
It is like a memory block transfer from PCI
Address Space to program data.
BIOS ROM
PCI memory
CPU
From the software point of view it is just a
move instruction.
System RAM
Each data transfer between bridges and busses is
transparent to the software.
1 M
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PCI Local Spaces
A PCI device can be configured as five memory
spaces with configurable address offset and range
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Memory space reserved for Medipix data
Not assigned
Local Space 4
Local Space 3
Not assigned
Local Space 2
Not assigned
Medipix matrix data read through parallel port
Local Space 1
Serial data
Local Space 0
Status
Control
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MPRS general schematic
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Motherboard

• Line drivers from Medipix to DAQ
• CMOS - LVDS drivers
• Power Supply, voltage regulator 3.3V 2.2V

34-pin I/O flat cables
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Motherboard picture
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DAQ PCI board

• PCI Universal card for 32-bit, 33 MHz slot.
• Main components
• PCI Bridge connection from PCI Bus to Local Bus
• Registers for output lines
• Buffers for input lines
• Address decode circuit
• Local Clock circuit
• Voltage regulator 3.3V
• Serial Eeprom

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PCI Board picture
Input connector
Output connector
Address decode
Output registers
Input buffers
Clock
3.3V reg.
Eeprom
Bridge
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PCI Board picture
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Software
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Utility software PCI board control panel

• Scan PCI bus
• Open device
• Read/write test
• Internal registers configuration

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Acquisition utilities

• Set the DACs
• Reset matrix data
• Set pixel registers
• Readout

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Image acquisition timing
Medipix2
time
Raw data memory
Readout
MPRS
2 ms
Start
MPRS
0 ms
Image reconstructionroutine
X-rays
Medipix photon counting phase
38 ms
Image Memory
Stop
0 ms
MPRS
Readout
MPRS
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Image reconstruction

• Any image processing is made by software after
  the acquisition, in particular
• Image reconstruction with deserialization and
  derandomization
• The total time is 256x8x14x32xTs 917504xTs
• where Ts is the period of the inner software
  loop.
• The reconstruction time depends on CPU speed
  however with a normal PC it lasts no more than
  10 ms
• The software does the reconstruction during the
  Medipix2 photon counting phase, so it does not
  slow down the process.

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Conclusions

• Parallel readout seems to be appropriate for the
  Medipix2 dynamic imaging acquisition.
• Actual PCs are convenient platforms for the
  image acquisition, processing, storage and
  visualization.
• Interfaces based on PCI bus are easy to develop
  and fast enough for our purposes.
• The hardware complexity is transparent for the
  software thanks to the bridges.
• Image reconstruction made by software simplifies
  MPRS hardware design.