Digilab 7-Segment Displays

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Digilab 7-Segment Displays

• Lab 4

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Lab 4
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Digilab2 DIO1 Boards
Four 7-segment displays
dig1
dig2
dig3
dig4
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Digilab2 Board Common Anodes
A1 A2 A3 A4
Pins
Pins
AtoG(6 downto 0)
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Digilab XLA
LEDs
7-segment displays
pushbuttons
switches
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Digilab Board
dig3
dig2
dig1
dig4
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Digilab XLA Board Common Anodes
A4 A3 A2 A1
Pins
Pins
CA CB CC CD CE CF CG
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7-Segment Decoder
a-g LOW to turn on segment
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7-Segment Decoder
library IEEE use IEEE.std_logic_1164.all   entit
y seg7dec is port (q in STD_LOGIC_VECTOR(3
downto 0) AtoG out STD_LOGIC_VECTOR(6
downto 0)) end seg7dec
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architecture seg7dec_arch of seg7dec is begin
process(q) begin case q is
when "0000" gt AtoG lt "0000001"
when "0001" gt AtoG lt "1001111"
when "0010" gt AtoG lt "0010010"
when "0011" gt AtoG lt "0000110"
when "0100" gt AtoG lt "1001100"
when "0101" gt AtoG lt "0100100"
when "0110" gt AtoG lt "0100000"
when "0111" gt AtoG lt "0001101"
when "1000" gt AtoG lt "0000000"
when "1001" gt AtoG lt "0000100"
when "1010" gt AtoG lt "0001000"
when "1011" gt AtoG lt "1100000"
when "1100" gt AtoG lt "0110001"
when "1101" gt AtoG lt "1000010"
when "1110" gt AtoG lt "0110000"
when others gt AtoG lt "0111000" end
case end process end seg7dec_arch
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Digilab2 Board Common Anodes
A1 A2 A3 A4
Pins
Pins
AtoG(6 downto 0)
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Multiplex displays
0
0
1
0
0 0 0 0 1 1 0
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Multiplex displays
0
0
0
1
0 0 0 1 1 1 1
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Multiplex displays
1
0
0
0
1 0 0 1 1 0 0
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Multiplex displays
0
1
0
0
0 1 1 1 0 0 0
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Lab 4
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signal clkdiv std_logic_vector(23 downto
0) begin -- Divide the master clock (50MHz)
down -- to a lower frequency. process
(mclk) begin if mclk '1' and mclk'Event
then clkdiv lt clkdiv 1 end if end
process   cclk lt clkdiv(17) -- 190 Hz
50MHz/218
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ctr2bit.vhd
-- A 2-bit up-counter library IEEE use
IEEE.std_logic_1164.all use IEEE.std_logic_unsign
ed.all   entity ctr2bit is port (
clr in STD_LOGIC clk in STD_LOGIC
q out STD_LOGIC_VECTOR (1 downto 0)
) end ctr2bit
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ctr2bit.vhd
architecture ctr2bit_arch of ctr2bit
is begin process (clk, clr) variable COUNT
STD_LOGIC_VECTOR (1 downto 0) begin if clr
'1' then q lt "00" elsif clk'event and
clk'1' then COUNT COUNT 1 q lt
COUNT end if end process end ctr2bit_arch
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Lab 4
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Acode.vhd
library IEEE use IEEE.std_logic_1164.all   entit
y Acode is port ( Aen in
STD_LOGIC_VECTOR (3 downto 0) Asel in
STD_LOGIC_VECTOR (1 downto 0) A out
STD_LOGIC_VECTOR (3 downto 0) ) end Acode
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architecture Acode_arch of Acode is begin
process(Aen, Asel) begin A lt "0000"
case Asel is when "00" gt if Aen(1)
'1' then A lt "1000" end
if when "01" gt if Aen(2) '1'
then A lt "0100" end if
when "10" gt if Aen(3) '1' then
A lt "0010" end if when
others gt if Aen(4) '1' then
A lt "0001" end if end case end
process end Acode_arch
Acode.vhd
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Lab 4
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-- System Library Components   component
IBUFG port ( I in STD_LOGIC O out
std_logic ) end component
U00 IBUFG port map (I gt bn, O gt bnbuf)